Zbigniew Chamski
b1f80bd7cf
Add back ICACHE/DCACHE CSRs, update Yaml+adocs. Fix design doc Makefile. ( #2937 )
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2025-04-16 15:19:48 +02:00
André Sintzoff
b46a7f2ce9
docs: add missing link to RST 60x design doc ( #2932 )
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2025-04-15 11:59:01 +02:00
André Sintzoff
823d7bd092
docs: generate HTML for 60x design doc ( #2930 )
2025-04-15 11:35:15 +02:00
JeanRochCoulon
0999d3480d
Generate cv32a60x design document ( #2924 )
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Fix cv32a65x design document
Update CVXIF design documentation
Remove DCACHE/ICACHE CSRs from spec, doc, and config files.
Remove cache description from cv32a60x
Update OBI interfaces specification for cv32a60x
2025-04-15 09:42:16 +02:00
Jalali
e4a8ffb1f6
Code coverage : exclude second instanciation ( #2925 )
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of instr_scan and cva6_fifo_v3
Signed-off-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
2025-04-14 14:30:24 +02:00
Mike Thompson
f5b8c746f2
Reinstate docs build for 07_cv32a60x ( #2923 )
2025-04-14 13:53:35 +02:00
JeanRochCoulon
33a66ee5b9
Fix some TO_BE_COMPLETED IO description ( #2918 )
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2025-04-11 15:25:42 +02:00
Yannick Casamatta
cb27242e17
Clean up irrelevant FIXME/TODO ( #2915 )
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2025-04-11 12:59:41 +02:00
Yannick Casamatta
5355c76147
OBI: fix prot default value according to standard, and drive all parity signals ( #2913 )
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2025-04-10 16:07:15 +02:00
André Sintzoff
a220a54942
config_pkg.sv: fix typo (for doc rendering) ( #2909 )
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remove one dash
2025-04-09 15:34:06 +02:00
Zbigniew Chamski
440062b9c0
Update RS3 RType and CUS_CADD instructions to respect to CVXIF instruction. Fix forwardings issues. ( #2902 )
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* Update RS3 RType and CUS_CADD instructions to respect to CVXIF instruction. Fix forwardings issues.
In RS3 RType rd == rs3. To stay uniform with tools and RISCV UNPRIV, rd == rs1 in CUS_CADD.
* Bump core-v-verif
* CVXIF agent : aligned cvxif agent to new instructions spec
---------
Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Co-authored-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
2025-04-07 12:30:30 +02:00
Ayoub Jalali
d84b12938e
bump core-v-verif
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2025-04-03 09:57:32 +02:00
Casamatta Yannick
11ce298969
Clean up irrelevant FIXME/TODO
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2025-04-02 12:00:48 +02:00
Jalali
8d89206604
Verif: don't bind obi_amo_if if atomic extension not supported ( #2896 )
2025-04-02 11:58:38 +02:00
Valentin Thomazic
57771bbbe8
fix merge report job in gitlab ci ( #2897 )
2025-04-02 11:32:28 +02:00
André Sintzoff
122f6fcf92
spyglass/reference_summary.rpt: no more WarnAnalyzeBBox ( #2891 )
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2025-04-01 15:36:48 +02:00
Valentin Thomazic
37049ee788
add macros for assertions else clauses ( fix #1624 ) ( #2888 )
2025-04-01 12:25:36 +02:00
Guillaume Chauvon
7c1b94525d
Remove unread module and its instanciations ( #2887 )
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2025-03-31 15:43:47 +02:00
Guillaume Chauvon
2d3532e192
Hotfix 2885: Condition on RVU ( #2886 )
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Condition on RVU because you can have RVU with M mode but not RVS without RVU
2025-03-31 15:41:53 +02:00
Guillaume Chauvon
31dd1d232b
Increase code coverage priv_lvl in csr_regfile ( #2885 )
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
2025-03-31 12:51:11 +02:00
Guillaume Chauvon
c3507a1223
Fix multiple warning in Spyglass (mainly read but not set) ( #2883 )
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* csr_regfile.sv: Fix Spyglass Errors and Warning
* Spyglass: Update reference summary
2025-03-28 16:06:16 +01:00
Ayoub Jalali
605528474f
Bump core-v-verif
2025-03-28 15:53:10 +01:00
Zbigniew Chamski
542d1b5a80
Fix #1625 : Allow unmapped memory accesses in Spike for cv32a60x/cv32a65x. ( #2882 )
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Enable silent fetch/load of zeroes when accessing unmapped memory locations in Spike:
* Bump CVV to use Spike supporting unmapped accesses when core-specific parameter allow_unmapped_mem_access is set to True.
* Add allow_unmapped_mem_access: True field to core-specific section of CV32A60X and CV32A65X Spike Yaml files.
2025-03-28 12:35:36 +01:00
Valentin Thomazic
55b5865076
Revert "fix merge report script in gitlab ci ( #2875 )" ( #2879 )
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This reverts commit 69e4e8d5c5
2025-03-28 00:32:48 +01:00
André Sintzoff
66dac30e5f
frontend.sv: fix obi fetch align ( #2877 )
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OBI protocol requires that addr field is align with BE field, Fetch bus performs only full BE access, and until now provides next PC in addr field, next pc is not necessary align so in that case we are not compliant to OBI protocol.
This PR fixes by force to zero LSB of addr obi.
---------
Co-authored-by: Casamatta Yannick <yannick.casamatta@thalesgroup.com>
2025-03-27 11:08:02 +01:00
Valentin Thomazic
69e4e8d5c5
fix merge report script in gitlab ci ( #2875 )
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avoid retrieving pull requests when running the scripts for gitlab pipelines
2025-03-27 00:03:49 +01:00
Zbigniew Chamski
4c0e243740
[riscv-config] Mark all PMP registers as RO const zero. ( #2874 )
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Since the CV32A60X and CV32A65X do not have a PMP unit, specify all PMP registers as read-only constant zero in riscv-config 'ISA' files.
2025-03-27 00:02:40 +01:00
Guillaume Chauvon
dc91a02090
Spyglass: Update ref summary and waiver file
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2025-03-26 15:39:54 +01:00
Guillaume Chauvon
ff28b6239a
Fix some Spyglass Errors and Warnings
2025-03-26 15:39:54 +01:00
Guillaume Chauvon
f4c26fcc55
Improve CC for MTVEC csr
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2025-03-25 16:50:16 +01:00
André Sintzoff
768f5664b7
docs: fix TODOs in machine.adoc ( #2863 )
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according to latest CV32A60X configuration
2025-03-24 17:20:12 +01:00
Ayoub Jalali
babf1d15ac
CVA6 Tb : bind cvxif assertion with propere parametres
2025-03-24 13:53:30 +01:00
André Sintzoff
592e799bf0
csr_regfile.sv: improve code coverage (NrPMPEntries) ( #2859 )
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by adding if (CVA6Cfg.NrPMPEntries != 0)
2025-03-21 16:53:21 +01:00
JeanRochCoulon
4bdd57cdc2
[HOTFIX] Fix 2855 PR ( #2858 )
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by updating csr_regfile.v
2025-03-21 16:42:32 +01:00
André Sintzoff
6e4ac43e1f
multiplier.sv: improve code coverage ( #2853 )
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in mult.sv, mul_valid_op (becoming mult_valid_i in multiplier.sv) is
already computed with
&& (operation_i inside {MUL, MULH, MULHU, MULHSU, MULW, CLMUL, CLMULH, CLMULR})
Therefore, this operation is useless in multiplier.sv
2025-03-21 14:59:34 +01:00
Guillaume Chauvon
035a01466e
Fix c87b3e6ad ( #2856 )
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Fix issue_read_operand modification done in commit c87b3e6
2025-03-21 14:59:09 +01:00
André Sintzoff
38f44dad7c
csr_regfile.sv: use better signal name (CSR_MTVEC) ( #2854 )
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Vectored instead of misleading DirVecOnly
2025-03-21 14:56:44 +01:00
JeanRochCoulon
ebcb43a669
To improve CC ( #2855 )
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Improve CC by solving for loop in csr_regfile.sv and conditioning drop signal by SpeculativeSb in cva6_pipeline.sv
2025-03-21 14:54:43 +01:00
Ayoub Jalali
37424d0adb
csr_regfile : condition RTL to improve code coverage
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2025-03-20 13:44:46 +01:00
Guillaume Chauvon
c87b3e6adc
Various improvement for code coverage ( #2846 )
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decoder improvement, removing of CVXIF RAW, store_buffer improvement
2025-03-20 12:19:01 +01:00
Valentin Thomazic
42eea3fe38
Fix cv32a60x thales ci badge ( #2843 )
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2025-03-19 11:59:01 +01:00
Valentin Thomazic
811ea7a2ee
push reports to cv32a60x pipelines when applicable ( #2842 )
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Pipeline triggered by commits coming from cv32a60x branch will be pushed to the cv32a60x dashboard.
Also adds a wait time before commenting the pr to wait for the dashboard generation.
2025-03-19 11:14:58 +01:00
Guillaume Chauvon
dbdb4b75e6
cvxif_compressed_if_driver.sv: Improve code coverage
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2025-03-18 15:07:00 +01:00
Zbigniew Chamski
b7ca642dac
Bump CVV ( #2593 , #2595 ).
2025-03-18 13:28:55 +01:00
Jean-Roch Coulon
79ad41dc44
Improve CC
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2025-03-17 10:48:52 +01:00
Jalali
931152d205
FIx uvm seed for regression tests (light tests) ( #2828 )
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Use only one uvm seed (=1) for light tests, to fix timeout error due to obi delays randomization
2025-03-14 22:43:12 +01:00
Zbigniew Chamski
c2794df8e6
[CV32A6*X] Disable Zifencei across the verification infrastructure. ( #2822 )
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This MR implements the non-RTL part of CVA6 project changes needed for #2734 :
* changes to scripts
* changes to configuration files
* turn off Zifencei support in RTL configuration.
2025-03-13 06:12:47 +01:00
JeanRochCoulon
dcee5b9cbb
Improve Code Coverage ( #2826 )
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When resolved_branch_i.is_mispredict is 1, resolved_branch_i.valid is 1 (see branch_unit.sv code).
Simplify code to increase code coverage
2025-03-12 23:24:22 +01:00
Jalali
f36651b857
Condition RTL to improve code coverage ( #2815 )
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* decoder.sv : mideleg isn't supported only if RVS is enabled
* commit_stage.sv : commit_drop is high only if we support supercalar
2025-03-07 22:00:47 +01:00
André Sintzoff
9cd5c7711f
report_spyglass_lint.py: reject any increase in reported messages ( #2816 )
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this will avoid any regression in linting
2025-03-07 21:59:23 +01:00
