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Author	SHA1	Message	Date
valentinThomazic	53b51ac5a7	do not use tandem on test suites in ci (#2463)	2024-08-26 23:56:51 +02:00
Côme	339d3dd851	Increase code coverage on second ALU by removing branch logic (#2362)	2024-08-26 17:32:24 +02:00
Côme	064cec2066	fix missing ZCMP condition in commit stage to increasse Code Coverage (#2459)	2024-08-24 11:48:36 +02:00
Côme	4c36aafaf0	fix CI (#2460) ... * fix .gitlab-ci.yml * Update report_tandem.py	2024-08-23 11:34:17 -04:00
EasyIP2023	37b58243fa	docs: expand wy-nav-content width to edge of screen (#2452)	2024-08-22 18:10:19 +02:00
valentinThomazic	28affa2346	[CI] use spike tandem on smoke-tests (#2438)	2024-08-22 17:04:48 +02:00
Côme	76e5b40961	fix single-step which was x in cv32a65x config and fix mcycle for double commit (#2369)	2024-08-22 12:03:20 +02:00
dependabot[bot]	12f41b52ac	Bump verif/core-v-verif from e06bd57 to 628ba12 (#2456)	2024-08-20 08:37:35 +02:00
André Sintzoff	051ba348f9	spyglass: remove WRN_1024 warnings (#2448)	2024-08-19 15:44:30 +02:00
Zbigniew Chamski	89eb77a249	[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. (#2436)	2024-08-19 11:09:32 +02:00
André Sintzoff	834e3e74d5	spyglass: ignore some multiple assignment W415a warnings (#2446)	2024-08-14 14:17:38 +02:00
JeanRochCoulon	d2889fa174	Display number of cycles at test termination (#2443) ... Reported by RVFI_tracer module	2024-08-13 17:12:13 +02:00
André Sintzoff	e5618977d1	spyglass: move assignments in if clause as only used there (#2444)	2024-08-13 17:11:10 +02:00
Guillaume Chauvon	4f45b575aa	Add ariane_peripherals and testharness to fpga_filter (#2445)	2024-08-13 16:18:11 +02:00
Jalali	9b576c1200	Configure uvm scoreboard to fix 64 issue (#2440)	2024-08-13 09:16:54 +02:00
André Sintzoff	af4e3744d4	spyglass: remove useless assignments (#2439)	2024-08-12 15:06:39 +02:00
MarioOpenHWGroup	4b51643826	TANDEM Configuration fixes (#2420)	2024-08-09 12:34:40 +02:00
valentinThomazic	7435cb310e	fix Spyglass job falsely reporting fail (#2435)	2024-08-07 12:12:38 +02:00
André Sintzoff	3059b1cb25	update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2434) ... since last riscv-isa-manual update (CVA6 commit 0bd8b8693)	2024-08-07 11:52:07 +02:00
xiaoweish	0c60bc6e3d	Add debug_test to cva6 (#2339)	2024-08-02 08:50:50 +02:00
JeanRochCoulon	ce4b25c51a	[HOT FIX] fix is_inside_execute (#2429) ... fix #2385	2024-08-02 08:42:11 +02:00
JeanRochCoulon	14fd617455	Fix expected_synth.yml (#2428) ... Difficult to adjust it all the time !	2024-08-02 06:47:03 +02:00
Jalali	2e0a202440	Add check CSR counter in UVM scoreboard (#2427)	2024-08-02 00:20:47 +02:00
Asmaa Kassimi	12be3adb81	Solve some of W240 and W415a warnings increased by PMP entries (#2415)	2024-08-01 18:43:13 +02:00
Guillaume Chauvon	81671e39fa	Fixes and Update CVXIF non regression tests, regression and TB (#2424)	2024-08-01 16:06:24 +02:00
dependabot[bot]	6269f72b63	Bump verif/core-v-verif from bd42aee to e06bd57 (#2422)	2024-07-30 15:09:37 +02:00
Asmaa Kassimi	d4b62d7372	automate lint check process (#2414)	2024-07-30 09:22:13 +02:00
Zbigniew Chamski	4e9abb284c	[cv32a65x] Remove unsupported Zifencei from riscv-config ISA string. (#2419)	2024-07-30 09:20:33 +02:00
dependabot[bot]	bed9a17880	Bump verif/core-v-verif from 1e7f049 to bd42aee (#2418)	2024-07-30 07:08:21 +02:00
Zbigniew Chamski	8dcdf8fb56	[riscv-config] Add memory map entry to platform schema and to CV32A65X platform spec. (#2411)	2024-07-26 23:50:51 +02:00
slgth	6a649d6515	docs: more fixes (#2412)	2024-07-26 23:49:41 +02:00
slgth	2249202769	docs: multiple fixes (#2409)	2024-07-26 15:27:42 +02:00
AbdessamiiOukalrazqou	a4583a6e4d	[gen_from_riscv_config] improve readme file to support debug spec (#2406)	2024-07-26 15:25:54 +02:00
valentinThomazic	934823d89c	Add custom config in gitlab ci (#2405)	2024-07-26 15:04:40 +02:00
Guillaume Chauvon	211af02e5e	Separate RAW and WAW process to fix CVXIF with Superscalar (#2395)	2024-07-26 14:58:18 +02:00
Zbigniew Chamski	96b0508525	[riscv-config] Update PMP definitions in cv32q65x spec (#2401)	2024-07-25 22:06:51 +02:00
AbdessamiiOukalrazqou	b438a8ba8e	[gen_from_riscv_config] Improve the tool to support debug spec (#2398)	2024-07-25 20:07:45 +02:00
slgth	e9648eaf8c	Design documentation: AsciiDoc conversion (#2399)	2024-07-25 17:18:27 +02:00
Moritz Schneider	fd489a16fb	Fix off by one error in PMP length (#2394)	2024-07-25 12:08:53 +02:00
Asmaa Kassimi	631513eda8	Add RVU condition to increase coverage (#2396)	2024-07-25 12:03:38 +02:00
Somya Dashora	1e48237a7a	Update csr_regfile.sv to fix #2373 (#2374)	2024-07-25 09:54:13 +02:00
slgth	3deb95af21	cv64a6_mmu: add RISC-V ISA documentation to main page (#2393)	2024-07-25 08:37:27 +02:00
CoralieAllioux	335c91cc08	[Xcelium flow] Xrun compile fixes (#2389)	2024-07-25 07:37:43 +02:00
Asmaa Kassimi	4c48a60804	increase condition coverage in lsu, issue and commit stages (#2391)	2024-07-25 07:37:21 +02:00
Zbigniew Chamski	846e1a1269	[CI DEBUG] Track cause of failures in Spike version check. (#2360)	2024-07-24 23:56:04 +02:00
Côme	4ff16f9da3	set WtDcacheWbufDepth to 8 (#2390)	2024-07-24 23:54:26 +02:00
Asmaa Kassimi	14be0af7f0	solve simple lint errors (#2388)	2024-07-24 12:09:25 +02:00
dependabot[bot]	7181278223	Bump verif/core-v-verif from 20c2d30 to f42effb (#2381)	2024-07-23 23:21:25 +02:00
Jalali	118f353f54	Exclude page fault exceptions if mmu isn't supported (#2387)	2024-07-23 19:40:49 +02:00
JeanRochCoulon	04ebfbd713	Disable PMA execute and nonidempotent features (#2385)	2024-07-23 15:57:22 +00:00