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Author	SHA1	Message	Date
valentinThomazic	d4809a7e2b	change required dhrystone cycles count value (#2386)	2024-07-23 17:55:43 +02:00
Côme	2acf5ba407	fix ex_stage synthesis (#2384)	2024-07-23 14:09:01 +02:00
AEzzejjari	4b2b6e2983	Enable HPDcache in the UVM config (#2379)	2024-07-22 22:53:15 +02:00
AbdessamiiOukalrazqou	aa4ced4a8a	[gen_from_riscv_config] improve readme file and requirements file to support spike (#2380)	2024-07-22 18:04:53 +02:00
valentinThomazic	77c6cc328d	fix CI regression testlists (#2378)	2024-07-22 17:29:25 +02:00
Côme	4a223bee46	decorrelate instr and addr depths in IQ (#2375)	2024-07-22 14:22:56 +02:00
JeanRochCoulon	8d413b7c54	doc PMA: cv32a65x is always idempotent and without caches (#2377)	2024-07-22 11:15:06 +00:00
dependabot[bot]	95049c4a3d	Bump verif/core-v-verif from 66cd091 to 20c2d30 (#2367)	2024-07-22 10:23:52 +02:00
AbdessamiiOukalrazqou	5f8605838e	[gen_from_riscv_config] fix access issues for PMP registers, improve Factorization algorithm , improve csr_updater.yaml, add spike support (#2372)	2024-07-21 22:39:50 +02:00
André Sintzoff	8c70976759	docs: use correct commit for riscv-isa-manual submodule (#2368) ... fix after 8fa590b5c	2024-07-15 12:42:07 +00:00
Jalali	6c0e3f82c5	Verif: Add load hazard instructions (#2354)	2024-07-15 12:39:52 +00:00
Asmaa Kassimi	8aa0f634f6	condition load and store modules (#2349)	2024-07-13 09:32:51 +02:00
Jérôme Quévremont	c4b4216981	Update cva6_requirements_specification.rst (#2364) ... Specify CV-X-IF version supported: 1.0.0. Mention of B extension (with includes the Zb* extensions, already in the specification). Make FENCE.T as a "should" instead of "shall" as we do not have plans to integrate it yet.	2024-07-12 18:14:26 +02:00
Côme	0cbd894a7a	update port and config docs (#2363)	2024-07-12 17:00:36 +02:00
jzthales	71653038d7	Doc lsu (#2359)	2024-07-12 16:49:02 +02:00
Jalali	da1c7477ed	Increase simulation time on CSR tests (#2361)	2024-07-12 16:21:04 +02:00
valentinThomazic	e53c669df1	Enable tandem on smoke-gen tests in ci (#2357)	2024-07-12 16:05:02 +02:00
Zbigniew Chamski	3e62b0b910	[Spike Yaml] HOTFIX: Add libyaml-cpp to preload list of RTL simulators. (#2358)	2024-07-12 11:52:01 +02:00
Guillaume Chauvon	8fa590b5c3	CVXIF 1.0.0 (#2340)	2024-07-12 10:53:18 +02:00
Côme	5fcc39dbee	remove round interval (#2353)	2024-07-11 17:35:03 +02:00
Mathieu Gouttenoire	18bfc238f9	Change sh to bash in toolchain-builder README (#2355)	2024-07-11 15:44:56 +02:00
Zbigniew Chamski	48ef515ba0	[Spike Yaml] Integrate Spike Yaml support. (#2304)	2024-07-11 08:37:37 +02:00
Côme	2dcb7417b4	make cv32a65x superscalar (#2348)	2024-07-10 23:33:49 +02:00
Asmaa Kassimi	214444cc93	csr_regfile lint error fix (#2346)	2024-07-10 13:13:26 +02:00
Jalali	dc9dc150e7	Increase supported PMP entries in UVM testbench (#2344)	2024-07-10 11:54:29 +02:00
JeanRochCoulon	58d490b461	Update PMP entry number from 16 to 64 (#2343)	2024-07-10 09:54:16 +00:00
Asmaa Kassimi	d9a7fdb836	condition branch_unit and alu (#2342)	2024-07-10 11:02:18 +02:00
LQUA	f44655809f	Add CV64A6_MMU core in user manual (#2324)	2024-07-09 16:49:31 +02:00
valentinThomazic	c50012ac76	Remove duplicate and out of date infos on verif readme (#2338)	2024-07-09 16:48:37 +02:00
Moritz Schneider	b6a3aa1b03	Fix non-standard usage of SystemVerilog (#2336) ... Strings cannot be initially assigned to an integer without a cast.	2024-07-09 10:39:52 +02:00
dependabot[bot]	7c351b3c8e	Bump verif/core-v-verif from 1173e7e to 2d9f96e (#2337)	2024-07-09 07:24:09 +02:00
Isaar Ahmad	0c58e39987	Update README.md : Updated gcc-toolchain-builder path (#2332)	2024-07-06 18:54:53 +02:00
Côme	37d93a3758	superscalar: do not issue CSR with another instruction (#2329)	2024-07-05 23:49:44 +02:00
André Sintzoff	51114ee0a1	machine.adoc: add missing table (#2331) ... For CVA6, add table: Encoding of A field in PMP configuration registers	2024-07-05 23:49:20 +02:00
Moritz Schneider	6044454a07	Fix index calculation for PMPCFG CSR write logic (#2330)	2024-07-05 22:56:27 +02:00
Asmaa Kassimi	67dba2cad3	condition csr_regfile.sv (#2310)	2024-07-05 14:14:01 +02:00
Côme	4df49a6b0f	superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322)	2024-07-05 14:09:48 +02:00
valentinThomazic	051a2f94ff	Retry FPGA boot in CI when failed (#2325)	2024-07-05 12:06:42 +02:00
André Sintzoff	0bd8b8693a	update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323) ... since last riscv-isa-manual update (CVA6 commit 105d3601b): - minor documentation changes - use of docs-resources submodule inside riscv-isa-manual - requires asciidoctor-lists	2024-07-05 12:06:16 +02:00
Jalali	2616d5e649	add UVM interrupt agent (#2309)	2024-07-05 11:54:34 +02:00
Guillaume Chauvon	9900d5fd19	Fix benchmark.sh with correct GCC options and order (#2313)	2024-07-05 11:52:27 +02:00
Moritz Schneider	246961b3c3	Increase max num PMPs to 64 (#2279)	2024-07-04 14:09:37 +02:00
Mathieu Gouttenoire	d98ac1490a	New toolchain builder script for GCC and LLVM (#2320) ... * Move build-toolchain.sh * New toolchain builder script for GCC and LLVM	2024-07-04 09:46:41 +02:00
LQUA	66caecdfe6	Add RISCV documentation for cv64a6_mmu (#2315)	2024-07-03 17:24:07 +02:00
Jalali	702fedf23f	Fix issue #2479 #2468 (#2318)	2024-07-03 17:14:15 +02:00
Asmaa Kassimi	ace1643e91	Add lambda function to sort lint summary according to severity (#2316)	2024-07-03 16:46:30 +02:00
Jalali	f18bac51b3	Bump CVV to fix issue 2484 (#2302)	2024-07-02 17:41:23 +02:00
Jalali	9ebe42f033	Add illegal instruction to cover corner case in decoder (#2307)	2024-07-02 17:40:45 +02:00
Asmaa Kassimi	3874c41320	fix lint errors in csr_regfile.sv (#2306)	2024-07-02 15:36:04 +02:00
dependabot[bot]	0721ebb609	Bump verif/core-v-verif from 0e97e74 to 4531071 (#2305)	2024-07-02 08:23:22 +02:00