Guillaume Chauvon
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a5152b03a5
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Add support for cv32a65x dedicated synthesis (#2178)
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2024-06-04 10:58:09 +02:00 |
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Côme
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83d94bbb69
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transform rvfi types into macros (#1921)
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2024-03-12 17:34:27 +01:00 |
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Yannick Casamatta
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1dec79464e
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add csr in rvfi (#1833)
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2024-02-24 00:10:23 +01:00 |
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Nils Wistoff
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3833439fb7
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fpu: ⬆️ Update FPU version (#1102)
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
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2023-04-14 23:53:45 +02:00 |
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JeanRochCoulon
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710da10297
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Remove RVFI_TRACE/RVFI_MEM ifdef verilog directive (#1141)
To allow to remove optionally ports, ifdef directive are kept in cva6_config package.
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2023-04-11 07:49:59 +02:00 |
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JeanRochCoulon
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31948853c6
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Replace WT_DCACHE define by CVA6ConfigCacheType localparam (#1127)
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2023-03-21 14:18:18 +01:00 |
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Zbigniew Chamski
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c288812008
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Enable RVFI_MEM support at gate level. (#1113)
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2023-03-12 22:17:51 +01:00 |
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JeanRochCoulon
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adf99b5304
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Remove email adress to avoid email robot spaming (#1094)
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
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2023-03-06 06:57:25 +01:00 |
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JeanRochCoulon
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4b33e69a10
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Use only one Flist for all configurations (#1012)
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2022-12-13 09:31:26 +01:00 |
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Zbigniew Chamski
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8a5898dce4
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Vendorize CVA6 core submodules (common_cells, FPU with related sub-modules) (#1007)
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2022-12-09 11:07:12 +01:00 |
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Guillaume Chauvon
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1e2ec41cc0
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Update to synthesis and simulation gate flow (#947)
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2022-09-01 10:18:13 +02:00 |
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Guillaume Chauvon
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909d85a56c
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Fix tc_srams paths (#892)
* cva6_synth.tcl: fix set_input_delay and set_output_delay tc_sram paths
* ariane_tb.cpp;.sv: [Fix tc_srams] change path for user memory preload
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
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2022-05-30 22:50:50 +02:00 |
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JeanRochCoulon
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2c3d0f741d
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fix gate simulation broken by tc_sram_wrapper insertion (#871)
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2022-05-11 06:32:44 +02:00 |
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JeanRochCoulon
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35f430d8c6
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Replace SyncDpRam by tc_ram (#861)
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
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2022-04-28 20:13:55 +02:00 |
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Gchauvon
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e4b48a794b
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cva6_synth.tcl: add missing hierarchy for I/O memory delays and timing reports (#826)
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
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2022-02-17 14:41:42 +01:00 |
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JeanRochCoulon
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b242c3f80b
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pd: Add Synopsys DC synthesis target (#775)
* riscv_pkg.sv, cva6_imac_sv_config_pkg.sv: define FPU_EN as platform parameter
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* scripts to make ASIC synthesis
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* README.md: update synthesis and gate simulation descrption
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Update README.md
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/Makefile
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/cva6_read.tcl
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/cva6_read.tcl
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/cva6_synth.tcl
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/scripts/dc_setup.tcl
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/scripts/dc_setup_filenames.tcl
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Update pd/synth/scripts/gateAnalysis.py
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* rename CVA6ConfigFpuen into CVA6ConfigFpuEn
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Revert "Update pd/synth/cva6_read.tcl"
This reverts commit 5e4433081d.
* cva6_read.tcl: read synthesis result
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* define CACHE RAM INPUT_DELAY and OUTPUT_DELAY
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* renale gateAnalysis.py
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix input and output delays
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* gate_analysis.py reformatted thanks to Black
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* fix INPUT and OUTPUT DELAY setup
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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2021-12-13 19:17:43 +01:00 |
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