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146 commits

Author SHA1 Message Date
Côme
7b3054156e
Add CVA6 performance model (#2880)
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2025-03-28 14:50:12 +01:00
Valentin Thomazic
d94db10fb1
Minor dashboard-related adjustement (#2841)
* wait for dashboard generation before commenting PRs with pipeline report link.
* change dashboard link and badge

---------

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-03-19 11:14:10 +01:00
Valentin Thomazic
dfdc72cb5a
Enable gdb on toolchain builder (#2789)
As discussed in #2775 (comment) , this pr enables gdb back on the toolchain build scripts. It also updates the README to use the current toolchain name for the gdb section.
2025-02-25 07:09:27 +01:00
Pascal Cotret
9d039197d1
update smoke tests file names (#2736)
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Related to issue #2715

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-01-23 17:54:21 +01:00
AngelaGonzalezMarino
bca4e1544f
update readme with information how to generate bitstream for agilex 7 (#2690)
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2025-01-08 12:01:33 +01:00
Valentin Thomazic
820a8c6e01
Fix documentation build (#2641)
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* Fix rtd yaml
* add rtd badge to readme
2024-11-29 14:37:50 +01:00
Valentin Thomazic
51543db607
fix readme links (#2575)
Fix dashboard and label links in README (see #2554 )
2024-11-04 17:33:19 +01:00
Jean-Roch Coulon
9cfadbeded Create dedicated linker scripts for cv32a65x configuration. When another configuration is targeted, the default linker script is used (config/genxxx/linker/link.ld). When hwconfig is targeted, linker scripts are recopied into hwconfig directory.
Keep only one unique linker script: link.ldi. Remove test.ld file.
2024-10-23 18:24:38 +02:00
JeanRochCoulon
45eaace82b
Revert "Multicommits to shorten smoke-tests duration, to declare VLEN as para…" (#2564)
This reverts commit 0877e8e446.
2024-10-23 18:12:49 +02:00
JeanRochCoulon
0877e8e446
Multicommits to shorten smoke-tests duration, to declare VLEN as parameter, to improve coremark results, to implement spike.yaml/linker dedicated to 65x (#2563)
- FIX: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
- Declare VLEN as new CVA6 parameter
- smoke-hwconfig: run with vcs-uvm and use return0 tests to speed-up CI light stage timing execution
- Use dedicated linker scripts for 65x configuration.
- Use dedicated spike.yaml for 65x configuration.
- Set BHTEntries=128, cache=WT, scoreboard entries=8 to improve Coremark and Dhrystone results
- Run 4 iterations of coremark to improve results
2024-10-23 17:56:06 +02:00
Jérôme Quévremont
4a642d35d9
Resources and ecosystem (#2514) 2024-10-04 15:21:17 +02:00
valentinThomazic
004f819c14
Tandem for 65x (#2473) 2024-08-28 11:19:44 +02:00
valentinThomazic
28affa2346
[CI] use spike tandem on smoke-tests (#2438) 2024-08-22 17:04:48 +02:00
Zbigniew Chamski
846e1a1269
[CI DEBUG] Track cause of failures in Spike version check. (#2360) 2024-07-24 23:56:04 +02:00
Isaar Ahmad
0c58e39987
Update README.md : Updated gcc-toolchain-builder path (#2332) 2024-07-06 18:54:53 +02:00
JeanRochCoulon
c6f81d74c4
Remove parametrization Warning in README.md (#2011)
As th ebig change due to parametrization is over, I propose to remove the warning.
2024-04-08 10:33:28 +02:00
Zbigniew Chamski
d48c4b5b4e
Fix waveform generation using vcs-uvm. Add waveforms section to README. (#1827) 2024-02-13 12:08:18 +01:00
valentinThomazic
706daa0a3b
removed the usage of install-cva6.sh and add setup-env.sh (#1741) 2024-01-03 13:42:23 +01:00
valentinThomazic
4feab99254
Add prerequisites to README (#1738) 2023-12-27 16:36:23 +01:00
Yaotian Liu
e6a0d9e06a
fix: extra space in command (#1730) 2023-12-21 06:29:52 +01:00
valentinThomazic
6da3f465dc
make the readme quickstart more user-friendly (#1684) 2023-12-07 16:50:49 +01:00
Zbigniew Chamski
2745f3edcf
[GCC toolchain builder] Provide means of throttling parallel builds. (#1680) 2023-12-07 10:04:33 +01:00
valentinThomazic
aaac613c51
remove proxy kernel support (#1663) 2023-11-29 17:18:21 +01:00
Jérôme Quévremont
0a734159f9
Organizing acknowledgements in the repo (#1627) 2023-11-16 00:16:16 +01:00
Jérôme Quévremont
a34aca924e
Add funding acknowledgement (#1581) 2023-10-31 17:12:32 +01:00
JeanRochCoulon
bb80b3f245
Provide only one way to run simulation (#1505) 2023-10-06 09:45:17 +02:00
JeanRochCoulon
20dec24d1b
Supported Verilaotr version information (#1492)
Add information in the README.md to retrieve the supported Verilator version
2023-10-02 13:26:43 +02:00
Zbigniew Chamski
1683c818c4
Streamline installation process (Spike and toolchain variables, README file). (#1468) 2023-09-26 16:51:03 +02:00
Côme
7355fd7ce8
readme: use bash instead of sh (#1429) 2023-09-15 18:13:45 +02:00
Zbigniew Chamski
5c3e3d4545
Add GCC toolchain builder. Update README and .gitignore accordingly. (#1415) 2023-09-14 23:44:00 +02:00
Jean-Roch Coulon
1dd9773c8c Update README.md to give recommandations to setup environment and execute tests
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-09-07 11:38:34 +02:00
Pascal Cotret
9d6e434ee9
Fix VCD generation from Verilator model (#1341) 2023-08-24 06:08:16 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory (#1318)
* Clean-up README.md and top-level directory

This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>

* Re-name icache req/rsp structs

The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>

---------

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2023-07-28 08:32:48 +02:00
Jérôme Quévremont
bf6237ce7b
Update README.md (#1284) 2023-07-01 17:37:00 +02:00
JeanRochCoulon
037af687ee
Add banner to warm about parametrization work 2023-06-25 15:29:35 +02:00
JeanRochCoulon
59a1df031c
Remove DROMAJO (#1204)
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2023-04-24 23:05:53 +02:00
JeanRochCoulon
31948853c6
Replace WT_DCACHE define by CVA6ConfigCacheType localparam (#1127) 2023-03-21 14:18:18 +01:00
sébastien jacq
3d16fe20fd
Config cache fpga (#1000)
Create a FPGA configuration
Downsized caches from 4 to 2 ways in FPGA configuration
2022-11-25 13:56:15 +01:00
Mike Thompson
48af8dab6e
Update repo user docs (#841)
* Clarify scope of Verilator model

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Update repo user docs

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Update repo user docs

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* CORE-V not COREV

Signed-off-by: Mike Thompson <mike@openhwgroup.org>
2022-04-06 10:09:55 +02:00
Mike Thompson
00236be3d8
Clarify scope of Verilator model (#773)
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
2021-12-16 15:32:14 +01:00
JeanRochCoulon
b242c3f80b
pd: Add Synopsys DC synthesis target (#775)
* riscv_pkg.sv, cva6_imac_sv_config_pkg.sv: define FPU_EN as platform parameter

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* scripts to make ASIC synthesis

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* README.md: update synthesis and gate simulation descrption

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Update README.md

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/Makefile

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_read.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_read.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/cva6_synth.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/dc_setup.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/dc_setup_filenames.tcl

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Update pd/synth/scripts/gateAnalysis.py

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* rename CVA6ConfigFpuen into CVA6ConfigFpuEn

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Revert "Update pd/synth/cva6_read.tcl"

This reverts commit 5e4433081d.

* cva6_read.tcl: read synthesis result

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* define CACHE RAM INPUT_DELAY and OUTPUT_DELAY

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* renale gateAnalysis.py

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* fix input and output delays

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* gate_analysis.py reformatted thanks to Black

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* fix INPUT and OUTPUT DELAY setup

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
2021-12-13 19:17:43 +01:00
Andreas Kuster
206916d706
Add detailed simulation flow installation info & helper scripts (#740)
* Add information for verilator flow setup to README.md

* Prevent re-download if RISCV64_UNKNOWN_ELF_GCC already exists.
Use variable for archive version.

* Add RISC-V proxy kernel and bootloader install script

* Integrate tool installation into getting-started section

* Remove $ sign in command snippets to allow command copy & paste

* Add information for verilator flow setup to README.md

* Prevent re-download if RISCV64_UNKNOWN_ELF_GCC already exists.
Use variable for archive version.

* Add RISC-V proxy kernel and bootloader install script

* Integrate tool installation into getting-started section

* Remove $ sign in command snippets to allow command copy & paste

* Replace manual install command for riscv-pk by script

* Fix README.md merge conflict mismatches

* Fix script name

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2021-10-01 11:40:24 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU (#725)
* Initial repository re-organization (#662)

Initial attempt to split core from APU.

Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>

Compile `corev_apu` (#667)

* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

Add extended verification support (#685)

* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6

according to variant variable

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* add RVFI tracer and debug support

New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv

- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation

Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Move example_tb from cva6 to core-v-verif project

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Makefile: remove useless rule for vsim

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: add timescale definition when vsim is used

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: add vcs support (fix #570)

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* rvfi_tracer.sv: fix compilation error raised by vcs

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Makefile: use only 2 threads for verilator

when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Flist.cva6: cleanup for synthesis workflow

Thales synthesis workflow does not manage comments at end of lines

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Support FPGA generation

- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* Create cva6_config_pkg to setup 32- or 64-bit configuration

According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures

needed for dc_shell

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* riscv_pkg.sv: clean-up the cva6_config_pkg import

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>

* Add lfsr.sv to manifest

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Directory re-organzation

* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726)

into the new file organisation

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>

* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729)

Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>

Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
Florian Zaruba
33b7b672ee
ci: Switch to Github workflows (#689)
* ci: Switch to Github Workflows

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>

* README: Change build status

* Revert to Verilator 4.040

* verilator: Bump and mark DPI as thread-unsafe

* ci: Verilator v4.100

* verilator: Disable threading
2021-06-24 22:00:02 +02:00
Florian Zaruba
eaeef7da1a
verilator: Dot reference compilation issue (fix #583) (#585)
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2021-01-18 14:08:06 +01:00
Florian Zaruba
575cb445f8 README: Update with pointers to CVA6
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
2020-08-26 11:11:14 +02:00
Nils Wistoff
4d4c3f025d README.md: update image paths 2020-07-29 12:11:39 +02:00
Nursultan Kabylkas
2d81445209
verification: Add co-simulation with dromajo (#445)
* Summary: initial dromajo integration

* some changes to Makefile to enable `make verilate DROMAJO=1`
* adding ifdefs to ariane_tb.cpp to disable HTIF
* adding dromajo repo
* making dromajo repo a submodule

* syncing with upstream

* bumping to the latest dromajo commit

* Summary: adding DPI functions for cosim

 * added new file tb/dpi/dromajo_cosim.cc that contains
   all DPIs for dromajo to work
 * editted Makefile to see the above file

* Summary: fixing build issues

 * fixing syntax errors in dpi file
 * renaming dpi file due to name conflict with shared library
 * fixing path in Makefile to the shared dromajo lib

* bumping to the latest dromajo change

* Summary: loading checkpoint to bootrom

This change adds `+checkpoint=` argument to the verilator simulator
as well as corresponding changes to load the dromajo checkpoint into
the bootrom. Dromajo checkpoint bootcode contains series of csrw and
immediate loads to restore the architectural state of the processor.

dromajo_bootrom.sv
is a copy of a generated bootrom.sv file. This
file parses the verilog plusargs and loads the bootrom with the code
that is pointed by the +checkpoint.

csr_regfile.sv
Dromajo needs to start running the code in debug mode. The default
value of debug_mode_q was changed to 1.

* updating dromajo to the latest change

* Summary: sync main memories of dromajo and ariane

These changes load the checkpoint into the main memory of Ariane.
The checkpointed memory that is dumped from dromajo contains
(1) the binary and (2) the values of all stores that dromajo
globally performed before dumping the checkpoint.

dromajo_ram.sv
This file is a copy of SyncSpRamBeNx64.sv and was modified to parse
+checkpoint argument to load the memory from the path pointed by
the argument.

The remaining changes were introduced to instantiate the above file
when DROMAJO=1 flag is set.

* Summary: calling DPIs for cosimulation

This change introduces the calls to DPI functions that interface
with Dromajo.

* updating to the latest commit of dromajo

* disabling verbose output when preloading bootrom and mainram

* Summary: bug fix - update logic of `dcsr_d.prv`

This change was made per discussion with Florian via email. The
current versionincorrectly implements the update logic of
`dcsr_d.prv`.

The confusion came from the fact that the core should update its
`dcsr_d.prv` to the current running privilege level when entering
debug mode. I've attached a patch which, as you suggested, removes
the wrong update logic in the CSR write process and should now
correctly handle the update when entering debug mode
(4.9.1 Debug Control and Status of the debug specification).

* bump to the latest version of dromajo

* Summary: dromajo DPI change

This change:
 * Ariane doesn't commit ebreaks and ecalls so some workaround
   was encorporated
 * Proper exit(0) on cosim pass

* Summary: support for running binaries with dromajo

This change adds the ability to run the following command:
  `make run_dromajo BIN=\path\to\riscv\bin`

It automates the dromajo's checkpoint creation and runs the binary
on Ariane with dromajo cosimulation.

For this to work Ariane must be build with DROMAJO=1.

* changing dromajo recipe name to be consistent with existing names

* adding instructions on how to run cosim with dromajo

* Bump to release 0.6.2

* added license headers

* added more details about dromajo
2020-06-16 10:30:58 +02:00
Florian Zaruba
0830aec190 doc: Add Ariane publication 2019-12-03 14:18:10 +01:00
Florian Zaruba
48be94f822 Ariane 4.1.0 2019-03-18 11:51:58 +01:00