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494 commits

Author SHA1 Message Date
André Sintzoff
7cd183b710
verible-verilog-format: apply it on core directory (#1540) 
using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format
with default configuration

Note: two files are not correctly handled by verible
- core/include/std_cache_pkg.sv
- core/cache_subsystem/cva6_hpdcache_if_adapter.sv
 2023-10-18 16:36:00 +02:00
JeanRochCoulon
fb7064da00
Disable Zicond in cv32a6_embedded_config_pkg.sv (#1534) 2023-10-17 17:13:10 +02:00
Cesar Fuguet
7de1345291
Add the HPDcache as cache subsystem (#1513) 
Add the HPDcache as another alternative for the cache subsystem.
The HPDcache is a highly configurable L1 Dcache that mainly targets high-performance systems.
 2023-10-16 09:26:20 +02:00
Florian Zaruba
166c4b8ba1
[config] Reduce number of commit ports to one (#1531) 2023-10-13 14:30:18 +02:00
Florian Zaruba
5d6a5b5911
bender: Fix deleted file (#1530) 2023-10-12 16:25:17 +02:00
Nils Wistoff
589c3f1e6a
ci: Add regression tests for WB cache (#1523) 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2023-10-10 06:41:03 +02:00
Fatima Saleem
d3343f5210
resolving lint warnings (#1520) 2023-10-09 22:38:05 +02:00
Fatima Saleem
1e01596bbc
removing lint warnings in PMP Entry (#1510) 2023-10-08 14:17:14 +02:00
Fatima Saleem
38c949970e
Increased utilization of the speculative queue of store buffer (#1349) 2023-10-07 18:41:45 +02:00
AEzzejjari
ed5d42f1db
Code_coverage: Add conditions for the MMU (#1507) 2023-10-07 18:40:02 +02:00
Vincenzo Maisto
9046ef6d5a
Update mmu.sv for PMP violations tval value (#1498) 
Refere to issue #1490
 2023-10-05 13:16:39 +02:00
JeanRochCoulon
bb644bedbf
expected_synth.yml due to Zicond activation (#1494) 2023-10-03 06:24:43 +02:00
JeanRochCoulon
16f58c8e8a
[HOT FIX] fix synthesis job (#1487) 
A bad operation lead to update directly master while the idea was to create a PR.
The synthesis is broken. Try to fix it with this hot fix
 2023-09-28 12:25:53 +02:00
JeanRochCoulon
7c37510d57
Replace cva6 default cva6_config by synthesis config 
Default config shall be equal to Embbeded config to run synthesis.
 2023-09-28 11:57:32 +02:00
Florian Zaruba
93782ddfb5
Merge CVA6Cfg and ArianeCfg (#1321) 2023-09-28 11:41:38 +02:00
André Sintzoff
c136e8b226
Add mconfigptr CSR (fix #1480) (#1483) 
In version 1.12 of Machine ISA module (RISC-V privileged architecture
version 20211203), the mandatory CSR mconfigptr is defined.
 2023-09-27 23:17:58 +02:00
Abdul Wadood
47722a541e
ADD SUPPORT FOR Zcb EXTENSION (from Code Size Reduction, Zce) (#1431) 2023-09-26 16:26:31 +02:00
Yao Hsiao
283177c24a
Branch unit: Fix incorrect raising of instruction fetch misaligned exception (#1467) 2023-09-25 11:37:32 +02:00
AEzzejjari
4641acf9d2
Code_ coverage: Remove VCS coverage pragma for BitManip (#1469) 2023-09-23 00:22:29 +02:00
Fatima Saleem
e76eec7f25
Bypass misaligned address exception info in case of no MMU (#1457) 2023-09-21 10:05:20 +02:00
AEzzejjari
b952b0d7c3
Code_coverage: Add conditions for the FPU (#1442) 2023-09-19 18:24:40 +02:00
Fatima Saleem
2ac676d931
Add Zicond Extension support in CVA6 (#1405) 2023-09-15 08:19:50 +02:00
Florian Zaruba
91df62885f
Parametrize debug module (#1382) 2023-09-13 16:22:24 +02:00
JeanRochCoulon
de986ed17f
Hardwire the reserved bits of the PMPCFG CSR to 0 (#1368) 2023-09-11 18:22:59 +02:00
Fatima Saleem
8febe20849 updating the REG_ADDR_SIZE 2023-09-07 20:02:48 +05:00
Fatima Saleem
23098693d9 removed rename parameter from the config files 2023-09-07 20:02:48 +05:00
Fatima Saleem
8355a70ade removed rename block 2023-09-07 20:02:48 +05:00
Moritz Schneider
4c663fc164 Hardwire the reserved bits of the PMPCFG CSR to 0 
This realigns CVA6 with spike (#1346)

Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
 2023-09-07 14:35:03 +02:00
Domenic Wüthrich
03c14db797 [std_cache_subsystem] Fix AXI w_valid propagation when aw_ready is dependent on w_valid 2023-09-06 06:10:14 +00:00
Domenic Wüthrich
d45fda6179 [acc_dipsatcher] Add dcache request ports 2023-09-05 15:28:53 +00:00
Domenic Wüthrich
7092e4a81e [cva6] Connect acc dipatcher d$ ports to cache subsystem 2023-09-05 15:28:51 +00:00
Domenic Wüthrich
570c52992f [std_cache_subsystem] Add fourth dcache request port 2023-09-05 15:27:35 +00:00
Domenic Wüthrich
aad93781e5 [wt_cache] Add third read port 2023-09-05 15:27:00 +00:00
Cesar Fuguet
c087d1223f Support multiple outstanding load operations to the Dcache 
The ID in the request from the load/store unit must be mirrored by the
Dcache in the response. This allows to match a given response to its
corresponding request. Responses can be given (by the Dcache) in a
different order that the one of requests.

This modification introduces a pending load table that tracks
outstanding load operations to the Dcache. The depth of this table is
a parameter in the target configuration package.

Signed-off-by: Cesar Fuguet <cesar.fuguettortolero@cea.fr>
 2023-09-01 13:59:38 +02:00
JeanRochCoulon
c8202ae1ad
Decode AMOXOR_D (and similar instructions) only when XLEN=64bits (#1355) 2023-09-01 11:57:08 +02:00
JeanRochCoulon
434e55c457
Generate illegal opcode when execute LWU with XLEN=32 (#1344) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-08-28 21:55:37 +02:00
JeanRochCoulon
1db42ee8da
Add variant into CVA6 parameter (#1320) 
* Variane as CVA6 parameter

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* fix FPGA build

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Fix tipo in cva6.sv

* fix lint warnings

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Fix is_*_fpr functions

* remove blank lines

* set IsRVFI out of CVA6Cfg

* define config_pkg

* Fix ariane_pkg comments

* Fix Lint from André's feedbacks

* Fix parameter transmission

* Fix replace CVA6Cfg by CVA6ExtendCfg in cva6.sv

* fix add CVA6Cfg in instr_queue, instr_scan and pmp parameters

---------

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: ALLART Come <come.allart@thalesgroup.com>
 2023-08-22 14:04:06 +02:00
Côme
18766f186e
fix prediction shift for BHT and BTB (#1337) 
* add labels to if/else blocks for branch prediction

* add labels to if/else blocks for caches

* fix prediction shift for BHT and BTB
 2023-08-18 10:26:26 +02:00
Moritz Schneider
306973a386
Fix index calculation for locked PMP csr logic (#1335) 
Fixes #1332
Superseeds #1334

Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
Co-authored-by: Ömer Güzel <omer.guzel@agu.edu.tr>
 2023-08-15 11:29:31 +02:00
Enrico Zelioli
49d1262512
[FIX] m/sret optimization (#1333) 
Remove m/sret stall penalty by removing the icache miss

Co-authored-by: Enrico Zelioli <ezelioli@student.ethz.ch>
 2023-08-14 14:24:01 +02:00
Hossein Askari
7c94f9f92e
Adding configs for Polara (#1309) 2023-08-14 08:02:35 +02:00
Mohamed Aziz Frikha
1238079552
Add MSTATUSH register for RV32 (fix #1160) (#1328) 
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
 2023-08-13 23:20:07 +02:00
TulikaSi
bd5f1f99c0
Fix perfcounter #1237 PR 2023-08-13 23:16:33 +02:00
Florian Zaruba
dc103cd49f
Clean-up README.md and top-level directory (#1318) 
* Clean-up README.md and top-level directory

This removes the duplicate `scripts` and `util` directories. Furthermore
the README is condensed by collapsing the citation and adding the
CITATION file to the repository.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>

* Re-name icache req/rsp structs

The structs used to communicate with the icache have contained the
direction, which makes no sense for structs since they inherently don't
have any direction.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>

---------

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2023-07-28 08:32:48 +02:00
JeanRochCoulon
834b468096
Enable A extension (#1323) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-27 16:32:59 +02:00
Jalali
decabeb3f7
Add mode info in the CVA6 req to the co-proc (#1313) 2023-07-26 13:55:45 +02:00
Domenic Wüthrich
1a13d6c678
Add New Stall and Flush Signals to acc_dispatcher (#1317) 
* [lsu] Add external store buffer pending stall signal

* [controller] Add external acc request pipeline flush signal

* [frontend] Do not increment commit pc on flush if commit stage is halted

* [acc_dispatcher] Add new store buffer stall and flush pipeline ctrl signals

* [acc_dispatcher] Add top module passable config type and parameter

* [cva6] Pass on missing CVA6Cfg parameter to acc_dispatcher
 2023-07-26 13:50:38 +02:00
JeanRochCoulon
716d21c424
Define AXI as cva6 input parameters (#1315) 
* add axi parameters to cfg

* Move axi_intf.sv from core to corev_apu

* Move ariane_axi_pkg.sv from core to corev_apu

* Merge axi and l15 into noc

* Fixes to build and run openpiton

---------

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jonathan Balkind <jbalkind@ucsb.edu>
 2023-07-24 10:34:30 +02:00
Jalali
c467062a55
CVXIF : Add mode info in the CVA6 req to the coprocessor (fix issue #880) (#1298) 2023-07-20 13:41:45 +02:00
JeanRochCoulon
1ddbab33e9
Use CVA6Cfg as cva6 parameter (#1311) 
* Use CVA6Cfg as cva6 parameter

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Add information when defining CVA6Cfg type

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

---------

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-20 13:36:11 +02:00