Luca Valente
b45b52a38e
Parametrize MHPMCounterNum inside core/perf_counters.sv ( #1949 )
2024-03-25 11:37:54 +01:00
Bruno Sá
294ec96e76
Fix illegal instruction issue #1953 ( #1955 )
2024-03-25 07:26:42 +01:00
MarioOpenHWGroup
62bdf11594
Bump core-v-verif d94f0de and fix questa simulator ( #1915 )
2024-03-21 19:02:41 +01:00
Bruno Sá
86e1408666
Hypervisor extension ( #1938 )
...
Support 64bit H extension
2024-03-21 10:28:01 +01:00
Yannick Casamatta
9ecdaa1408
fix some bad assignments and lint warning related to RVFI feature ( #1947 )
2024-03-20 10:37:51 +01:00
dependabot[bot]
d0f411d178
Bump core/cache_subsystem/hpdcache from 8a13ec4 to 645e422 ( #1942 )
2024-03-18 20:30:40 +01:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
...
This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
André Sintzoff
f0887e4ec5
commit_stage.sv: add condition before Zcmp code ( #1932 )
2024-03-15 18:16:33 +01:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Michael Platzer
91fe64b119
acc_dispatcher: Allow single-stepping of commit stage ( #1920 )
...
Gives the accelerator dispatcher the ability to single-step the
commit stage, which avoids retiring instructions on another
commit port than port 0.
2024-03-12 21:42:06 +01:00
JeanRochCoulon
57f062bd85
Add Caches submodule description in Design Doc ( #1923 )
2024-03-12 17:40:05 +01:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
JeanRochCoulon
301f18a5f4
Improve FRONTEND description ( #1914 )
2024-03-11 12:52:35 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
Yannick Casamatta
bc41a0b7fb
Modify rvfi probes for param change ( #1900 )
2024-03-07 18:34:27 +01:00
Côme
13dfa744d2
Parametrization step 1 ( #1896 )
2024-03-06 17:02:55 +01:00
Cesar Fuguet
9267d14f2e
hpdcache: update submodule, interface and parameters ( #1893 )
2024-03-05 22:24:44 +01:00
JeanRochCoulon
b3ae6e9362
Revert MMU ( #1890 )
...
* Revert "fix vcs simulation errors regarding hypervisor extension code (#1889 )"
This reverts commit 5ff5f164fb#1881 )"
This reverts commit 6a5863e71a#1876 )"
This reverts commit 9fb5db2555
2024-03-05 16:44:40 +01:00
AngelaGonzalezMarino
5ff5f164fb
fix vcs simulation errors regarding hypervisor extension code ( #1889 )
2024-03-05 14:36:08 +01:00
JeanRochCoulon
f9e6a22960
[HOTFIX] Fix ras.sv ( #1887 )
2024-03-05 13:32:39 +01:00
JeanRochCoulon
483ef90127
Update frontend module description ( #1882 )
2024-03-04 23:18:27 +01:00
AngelaGonzalezMarino
9fb5db2555
Mmu unify pr ( #1876 )
2024-02-29 22:03:56 +01:00
dependabot[bot]
5dceb0d57a
Bump core/cache_subsystem/hpdcache from 019e04f to 5dea9e0 ( #1877 )
2024-02-26 21:24:56 +01:00
Yannick Casamatta
1dec79464e
add csr in rvfi ( #1833 )
2024-02-24 00:10:23 +01:00
André Sintzoff
1474395869
decoder.sv: sfence.vma valid only if S mode supported ( fix #1866 ) ( #1869 )
2024-02-23 23:10:40 +01:00
JeanRochCoulon
f332688fc0
Complete Design Document ( #1865 )
2024-02-23 23:09:11 +01:00
André Sintzoff
71f57a38c2
csr_regfile.sv: no MENVCFG[H], MCOUNTEREN when no User mode ( fix #1843 ) ( #1861 )
2024-02-21 18:16:35 +01:00
André Sintzoff
3cdc903a3a
csr_regfile.sv: mcountinhibit only when PERF_COUNTER_EN ( fix #1844 ) ( #1860 )
2024-02-21 14:13:50 +01:00
dependabot[bot]
e70bcbd6e7
Bump core/cache_subsystem/hpdcache from 38b9318 to 019e04f ( #1857 )
2024-02-21 13:14:03 +01:00
Luca Valente
c84f979a15
Enable reads on CSR_HPM_COUNTERx ( #1824 )
2024-02-21 09:44:51 +01:00
Cesar Fuguet
5de7c6003a
hpdcache: bump new version of the submodule ( #1845 )
2024-02-19 18:17:40 +01:00
Cesar Fuguet
45ffb59980
fix: support of AMOs in cv32 configurations ( #1841 )
2024-02-18 23:30:41 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description ( #1832 )
2024-02-16 16:17:46 +01:00
Cesar Fuguet
00c0ff083a
hpdcache: bump new version of the submodule ( #1830 )
2024-02-13 18:19:16 +01:00
Nils Wistoff
6e8e2652b8
miss_handler: Fix AMO AXI ID mapping ( #1821 )
2024-02-09 23:14:47 +01:00
Nils Wistoff
f5d5becfdd
cva6_config: Add ZiCondExtEn localparam in v configs ( #1801 )
2024-02-09 13:47:20 +01:00
JeanRochCoulon
3f8649ec7e
Table builder for specification ( #1814 )
2024-02-08 10:54:47 +01:00
JeanRochCoulon
9d0c700f42
port_builder generates the table of ports ( #1805 )
2024-02-06 12:06:13 +01:00
CoralieAllioux
48ea9a1675
[Bugfix hpdcache] axi struct usage ( #1802 )
2024-02-05 18:51:44 +01:00
JeanRochCoulon
42b21b8034
Configure icache with 2 ways in cv32a65x ( #1800 )
...
set 2 ways of 2048 bytes
2024-02-01 16:47:05 +01:00
JeanRochCoulon
de5d0d7ed4
cv32a65x ( #1799 )
2024-02-01 13:11:45 +01:00
JeanRochCoulon
5378031681
Fix HPDCache to make it functional when ways=2 ( #1744 )
2024-01-30 21:50:12 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Guillaume Chauvon
13a4a092ab
Check that User mode is enable to set MPP to U-mode ( fix #1756 ) ( #1781 )
2024-01-25 10:05:57 +01:00
Côme
5742d2abc9
fix: add missing parameters in cva6_rvfi.sv ( #1771 )
2024-01-19 16:19:34 +00:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
Michael Platzer
78111aa5eb
config_pkg/csr_regfile: Add PMP entry rst vals & RO option ( #1769 )
...
This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
2024-01-17 17:41:38 +01:00
