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Author SHA1 Message Date
JeanRochCoulon
279ce9fb9b
Define RVFI as cva6 parameter (#1293) 2023-07-19 08:21:39 +02:00
Fatima Saleem
4d2a9fe032
Resolved Lint WIDTHEXPAND warnings(1/2) (#1303) 2023-07-18 11:06:09 +02:00
Domenic Wüthrich
a49ea21b85
[core] Move cache invalidation and fflag signals into acc_dispatcher (#1305) 2023-07-14 17:42:54 -07:00
Max Bjurling
622409a7e4
Fix infinite loop in std_cache_pkg::one_hot_to_bin (#1302) 
Use int unsigned for loop variable i to avoid wrapping before loop exit
condition is met.

Resolves bug #1301 (https://github.com/openhwgroup/cva6/issues/1301)

Co-authored-by: Max Bjurling <max.bjurling@planv.tech>
 2023-07-12 11:35:23 +02:00
Nils Wistoff
513bb91f82
Add Ara support (#1024) 
Support Ara via a custom, parametrised accelerator interface.

    cv64a6_imafdcv_sv39_config_pkg.sv enables V extension
    Pre-processor constant ARIANE_ACCELERATOR_PORT enables the interface between CVA6 and Ara. 
    FPU is bumped to a SIMD-compatible version

Backwards compatibility should be preserved. Once this is merged, we will change the reference of Ara upstream CVA6.

-----

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
 2023-07-10 17:12:59 +02:00
Fatima Saleem
018dbc4210
Resolved Lint WIDTHTRUNC warnings(1/2) (#1297) 2023-07-06 11:41:25 +02:00
Mohamed Aziz Frikha
3cb54a1623
Changing Addresses of ICACHE and DCACHE to solve #1202 issue. (#1290) 
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
 2023-07-01 17:27:57 +02:00
JeanRochCoulon
5284f828e4
declare cva6_cfg_t to pass the configuration through the hierarchy (#1287) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-01 17:24:21 +02:00
JeanRochCoulon
9be687ffe4
Add coverage pragmas to exclude BITMANIP code (#1288) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-06-30 11:45:18 -04:00
Fatima Saleem
5c51eb44bc
resolved ALWCOMBORDER lint warning (#1280) 2023-06-24 19:11:04 +02:00
JeanRochCoulon
29fef18311
Move wt_cache_pkg functions which depend on cva6 input paramaters (#1274) 
from wt_cache_pkg to dedicated modules.

This helps for the parametrization
 2023-06-24 13:29:07 +02:00
Fatima Saleem
f038c5831e
resolved latch lint warnings (#1268) 2023-06-23 08:28:30 +02:00
Nils Wistoff
4b2f4ca590
icache_axi_wrapper: Cast paddr to AxiAddr (#1277) 
Prevents a negative repetition multiplier if paddr width > AxiAddrWidth

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2023-06-21 23:39:10 +02:00
JeanRochCoulon
6c89fda0da
Remove (unused) std_no_dcache.sv file (#1266) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-06-20 17:17:33 +02:00
Lucas Deutschmann
bcff0ec90b
Introduced division fast paths for 0 and -1 to reduce the worst-case latency from WIDTH+2 to 1 (#1263) 2023-06-16 12:44:29 +02:00
Mohamed Aziz Frikha
71e7019834
Adding WPRI in spec : register MSTATUS (#1257) 
Co-authored-by: Frikha Mohamed Aziz <mohamed-aziz.frikha@thalesgroup.com>
 2023-06-08 22:42:04 +02:00
Lucas Deutschmann
b22e98be5d
Simplified expression for lzc_a_input, as the appended value has no effect if a!=-1 (#1254) 2023-06-08 12:15:52 +02:00
Chase Block
4263e20365
Fix amo offset forgetfulness (#1003) 
Co-authored-by: Charles Block <coblock2@illinois.edu>
 2023-06-08 07:18:55 +02:00
TulikaSi
ce7e30f6c0
Implementation of mcountinhibit and shadow CSRs (#1227) 
* Implementation of mcountinhibit and shadow CSRs
* Performance counter features
 2023-06-07 00:15:14 +02:00
André Sintzoff
99acdc271b
decoder.sv: ZEXT.H is valid only with Zbb bitmanip extension (fix #1234) (#1236) 
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
 2023-05-22 13:27:53 +02:00
cathales
3bab6ed815
perf: fix too strict restriction on FLU write-back (#1230) 2023-05-12 00:02:30 +02:00
MarioOpenHWGroup
8e39a17056
Adapt MMU to allow Questa compilation (#1232) 2023-05-11 23:05:35 +02:00
JeanRochCoulon
38437f895b
Enable Bit manipulation in cv64a6_imafdc_sv39 configuration (#1229) 
As B extension has demonstrated its effeciency, @jquevremont @fatimasaleem  I have activated the bit manipulation for the 64 bit configuration. Can you approve it ?
 2023-05-11 09:49:19 +02:00
JeanRochCoulon
59a1df031c
Remove DROMAJO (#1204) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-04-24 23:05:53 +02:00
Umer Imran
45259cfb6a
LINT: Initial changes for Lint warnings removal (#1158) 2023-04-24 08:22:56 +02:00
Zbigniew Chamski
a0893bce2b
Enable assertions in Verilator after migrating to Verilator v5. (#1185) 2023-04-19 09:35:40 +02:00
JeanRochCoulon
6c8b4a9566
Hotfix: fix indentation (#1197) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-04-17 22:55:15 +02:00
JeanRochCoulon
9535356cc1
Remove FORMAL directive from pmp module, as Verilator 5.0 supports assert (#1188) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-04-17 15:46:48 +02:00
Nils Wistoff
109f9e9ed3
ptw: Wait for rvalid on flush (#1184) 
When the PTW is flushed, we need any pending transactions to
complete before returning to the IDLE state. Currently, the PTW returns
to IDLE after one cycle. Remain in WAIT_RVALID until we have actually
received rvalid.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
Co-authored-by: Marcelo Orenes <movera@princeton.edu>
Co-authored-by: Hyunsung Yun <88669963+yuhysu@users.noreply.github.com>
 2023-04-16 21:28:37 +02:00
JeanRochCoulon
402ee6fdfc
Add AXI parameter in cva6 config, keep AXI master structs in ariane and slave in SOC (#1182) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
 2023-04-15 10:29:45 +02:00
Nils Wistoff
3833439fb7
fpu: ⬆️ Update FPU version (#1102) 
Co-authored-by: Matteo Perotti <mperotti@iis.ee.ethz.ch>
Co-authored-by: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
 2023-04-14 23:53:45 +02:00
JeanRochCoulon
c1df1da568
Declare rvfi package as common lib (#1179) 
Merge this PR. The Thales CI will be failed before updating core-v-verif with corresponding modification.
 2023-04-11 20:16:10 +02:00
JeanRochCoulon
710da10297
Remove RVFI_TRACE/RVFI_MEM ifdef verilog directive (#1141) 
To allow to remove optionally ports, ifdef directive are kept in cva6_config package.
 2023-04-11 07:49:59 +02:00
Nils Wistoff
e51eec2904
icache_axi_wrapper: Use AxiAddrWidth parameter (#1163) 2023-04-08 08:43:08 +02:00
Nils Wistoff
22ae096ddb
icache_axi_wrapper: Use AxiIdWidth (#1164) 2023-04-06 23:32:44 +02:00
TulikaSi
1a37f6cef1
64bit Performance counters (#1129) 2023-04-06 08:30:01 +02:00
JeanRochCoulon
d7491f4e28
Remove ifdef directives from IO cva6 module (#1153) 2023-04-04 07:52:10 +02:00
JeanRochCoulon
6d006558f1
Better control user AXI field when disabled (#1159) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-04-03 10:20:51 +02:00
JeanRochCoulon
640eb9dc67
Replace "operator" by "operation" to avoid C++ keyword names in the SV Code. (#1154) 2023-04-02 16:13:59 +02:00
JeanRochCoulon
74ea1be5fa
Add Bit manipulation in configuration (#1146) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-03-31 07:10:39 +02:00
JeanRochCoulon
7f4549f2be
Hotfix: set CVA6ConfigWtDcacheWbufDepth=8 to makes CI pass (#1139) 2023-03-25 07:10:05 +01:00
Cesar Fuguet
1b9f9c6763
Fix enum value comparison: it needs explicit cast to int (#1137) 
QuestSim requires to explicitly cast to integer an enumeration variable
when comparing against an integer constant.
 2023-03-24 22:37:39 +01:00
JeanRochCoulon
2a037ead17
Add new configuration target called cv32a6_embedded (#1138) 2023-03-24 17:16:17 +01:00
JeanRochCoulon
a8ec2aa868
Make MMU optional (#1136) 2023-03-24 16:13:00 +01:00
Cesar Fuguet
754ce59624
Add parameter on config file to define the width of the memory transaction ID (#1134) 
transaction ID between the I/Dcaches and the interconnection interface.
 2023-03-24 09:17:54 +01:00
JeanRochCoulon
0880ed02ad
Reduce the Dcache write buffer to save silicon area 2023-03-22 13:50:36 +01:00
sébastien jacq
ea4b51eac7
add WT dcache wbuff size configuration (#1130) 2023-03-22 12:28:08 +01:00
JeanRochCoulon
31948853c6
Replace WT_DCACHE define by CVA6ConfigCacheType localparam (#1127) 2023-03-21 14:18:18 +01:00
Cesar Fuguet
bc6128a0a0
Add ID signal to the request interface towards the data cache (#1121) 2023-03-19 22:32:20 +01:00
sébastien jacq
2c61865b18
Add shared TLB in 32 bits version (#1108) 2023-03-16 10:16:09 +01:00