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Author SHA1 Message Date
JeanRochCoulon
a9c7b4f1e1
Cvvdev/dev/formating4 (#920) 
Several format cleanings:
- split load_store_unit.sv to create lsu_bypass.sv
- add several "begin" and "end"
 2022-06-28 22:15:55 +02:00
Mike Thompson
767c465cfb
Introduce CV32A60X as first release (#916) 2022-06-28 14:04:06 +02:00
Guillaume Chauvon
66f158dea0
FPGA: Add scripts to boot linux fpga (#924) 
Signed-off-by: Guillaume Chauvon<guillaume.chauvon@thalesgroup.com>
 2022-06-28 09:59:51 +02:00
Yannick Casamatta
5d93a5c551
csr_regfile, instret signal bad lenght when 32bits (#918) 2022-06-28 09:56:37 +02:00
Yannick Casamatta
d315ddd0f1
gitlab-ci: add workflow for github pull request (#919) 2022-06-16 10:37:34 +02:00
JeanRochCoulon
38c58e50e8
Add cv32a60x platform configuration (#907) 2022-06-10 14:15:21 +02:00
Guillaume Chauvon
909d85a56c
Fix tc_srams paths (#892) 
* cva6_synth.tcl: fix set_input_delay and set_output_delay tc_sram paths
* ariane_tb.cpp;.sv: [Fix tc_srams] change path for user memory preload

Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2022-05-30 22:50:50 +02:00
Steffen Persvold
75807530f2
Add support for "high" counter CSRs in 32-bit mode (#847) 
* Add support for "high" counter CSRs in 32-bit mode

In 32bit mode MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH are
used to return the most significant 32-bit value of the counters
which are now always 64-bit wide.

Signed-off-by: Steffen Persvold <spersvold@gmail.com>

* Enable writing of MCYCLEH and MINSTRETH CSRs

Signed-off-by: Steffen Persvold <spersvold@gmail.com>
 2022-05-12 10:46:40 +02:00
Guillaume Chauvon
266f1386a1
cva6.sv: change RVFI exception signal (#873) 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-05-12 08:46:37 +02:00
JeanRochCoulon
2c3d0f741d
fix gate simulation broken by tc_sram_wrapper insertion (#871) 2022-05-11 06:32:44 +02:00
Guillaume Chauvon
b40bb3264b
wt_dcache_wbuffer.sv: remove init for user (#870) 2022-04-29 14:21:47 +02:00
Yannick Casamatta
8343d77888
gitlab-ci: Add variables for dashboard generation (#869) 2022-04-29 11:15:18 +02:00
DBees
c8e665c414
Create task.yaml 
Using same task issue yaml file as cva6-sdk
 2022-04-28 15:14:23 -07:00
JeanRochCoulon
35f430d8c6
Replace SyncDpRam by tc_ram (#861) 
Signed-off-by: Jean-Roch Coulon  <jean-roch.coulon@thalesgroup.com>
 2022-04-28 20:13:55 +02:00
jquevremont
c318548f22
CVA6 specification (reStructuredText format) (#855) 
* Create cva6_requirement_specification.rst

Restarting from scratch after Eclipse check fail.
Taken into account DBees review in PR #851.
Removed no-reset FPGA design style (risky, very limited gain in nowadays FPGAs).

* Add folder

Add folder

* Delete images

* Create ignore.txt

Workaround to create folder

* Add files via upload

CVA6 scope picture

* Delete ignore.txt

Remove file
 2022-04-28 08:13:29 -07:00
Gchauvon
fca6f42d74
Add script to generate custom configuration (#862) 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-04-22 10:08:05 +02:00
Gchauvon
34f63b4487
ariane_pkg.sv: Fix LOG2_INSTR_PER_FETCH when RVC is disable (#860) 2022-04-21 10:47:48 +02:00
JeanRochCoulon
56f8c9f5fe
Add user field between memory and caches (#857) 
* wt_dcche_wbuffer.sv: fix assert

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Many files: Add user between memories and cva6

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>

* Update std_nbdcache.sv

Make wb cache work

* Update setup.sh

Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-04-20 12:47:07 +02:00
sébastien jacq
0b61544da8
Dev dcache 32bits (#849) 
Reduce dcache data output width from 64 to 32 bits in cv32a6 configuration

Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
 2022-04-11 14:54:09 +02:00
Mike Thompson
48af8dab6e
Update repo user docs (#841) 
* Clarify scope of Verilator model

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Update repo user docs

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* Update repo user docs

Signed-off-by: Mike Thompson <mike@openhwgroup.org>

* CORE-V not COREV

Signed-off-by: Mike Thompson <mike@openhwgroup.org>
 2022-04-06 10:09:55 +02:00
sébastien jacq
c26bda3f7b
Make C extension optional (#833) 
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
 2022-03-25 16:01:17 +01:00
Luca Colagrande
8d893fb647
🐛 wb_dcache: Fix unaligned SC return data bug (#838) 
When a store-conditional fails due to a missing reservation,
by specification it must return a non-zero value.
Previously a value of 64'b1 was returned by the axi_adapter.
However, when an atop's address is non-64bit-aligned, the return data
has to be realigned. This realignment causes the lower half-word
being lost, and the return datum taking a value of '0.

This commit fixes the bug by returning {64{1'b1}} from the axi_adapter.
 2022-03-15 07:33:23 +01:00
Luca Colagrande
75250868eb
wb_dcache: Forward atomic transactions to AXI (#777) 
* wb_dcache: Forward "atomic transactions" to AXI

* Correct bugs

* Forward LR/SC atomics

* Fix CI

* miss_handler: Route AMO port through arbiter

* axi_adapter: Correct LOAD AMOs handling

Accept read data only after (or together) handshake on B channel

* Restore old ID

* Correct atop encodings

* Correct AMOs AXI ID

* Correct wb_dcache testbench

Previously not comparing AMOs at all! Due to amo_exp_resp being 'x

* Realign and sign extend 32b request rdata

* Use axi_pkg definitions for ATOPs encoding

* Remove whitespace

* wb_dcache: Style corrections

Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>

Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
 2022-03-09 16:33:37 +01:00
Yannick Casamatta
062ec9170a
Update Gitlab CI: new workflow, new jobs, code optimization (#832) 2022-03-04 08:11:35 +01:00
Gchauvon
e4b48a794b
cva6_synth.tcl: add missing hierarchy for I/O memory delays and timing reports (#826) 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-02-17 14:41:42 +01:00
Gchauvon
4c3dc25c0b
Makefile: Add register_interface/include directory to vcs compile option (#825) 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-02-16 16:32:12 +01:00
Moritz Schneider
34870aeea0
Fix reserved CSR write (#823) 
* Fix illegal write to PMPCFG

Reported by Flavien Solt (@flaviens)

Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>

* Cleanup CSR code for PMP

Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
 2022-02-11 11:15:02 +01:00
JeanRochCoulon
59d9836ee5
Makefile: Use init_testharness.do when VCS (#822) 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2022-02-11 10:51:46 +01:00
Nils Wistoff
fc817af76c tb_wt_dcache: Add AXI include dir 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-11 10:50:36 +01:00
Nils Wistoff
52c343c106 tb_cva6_icache: Add cf_math_pkg dependency 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-11 10:50:36 +01:00
Nils Wistoff
c419da3457 tb_wb_dcache: Provide ArianeCfg as cache parameter 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-11 10:50:36 +01:00
Nils Wistoff
22b67049f7 tb_wb_dcache: Add AXI includedir 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-11 10:50:36 +01:00
Nils Wistoff
8dd06b5f9e ariane_pkg: Prevent overflow during range_check 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-11 10:50:36 +01:00
Andreas Kuster
c72a9e5d56
Bump register interface to v0.3.1 (#819) 
* Bump register interface to v0.3.1

* Upgrade PLIC to upgraded register interface version v0.3.1

* Upgrade rv_plic submodule

* Add rv_plic upgrade to xilinx target. Fix indentations

* Try again (indentation)

* Add register_interface include
 2022-02-10 14:19:12 +01:00
Andreas Kuster
1e23ebac71
Add missing sources for questa simulation (#818) 2022-02-10 09:12:29 +01:00
RanjanThales
0065b28def
doc: Add cva6_ug_csr.adoc (#817) 
* added user_guide/CVA6_UG_CSR.adoc

* added docs/user_guide/CVA6_UG_CSR.adoc

* Update docs/user_guide/CVA6_UG_CSR.adoc

Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>

* Update cva6_ug_csr.adoc

Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
 2022-02-07 15:01:52 +01:00
Nils Wistoff
741e82133d
ariane_testharness/ariane_xilinx: Fix AXI ID width (#813) 
- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
  as they allow arbitrary AXI types

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-02-06 11:17:21 +01:00
Noah Huetter
da74358206
Remove debug module from devicetree (#806) 
* remove debug module from devicetree
* replace uart compatible string with one that uses the FiFos
* regenerate bootrom
* regenerate FPGA bootrom

Signed-off-by: Noah Huetter <huettern@iis.ee.ethz.ch>
Co-authored-by: Noah Huetter <huettern@iis.ee.ethz.ch>
 2022-01-31 15:37:48 +01:00
Florian Zaruba
944f915f96
csr: Fix wrong activation in vectored mode (#792) 
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2022-01-28 15:39:18 +01:00
Yannick Casamatta
bea9d5d1e6
Flist.cv64a6_imafdc_sv39_gate and update LIB_VERILOG path (#804) 2022-01-27 11:43:03 +01:00
Yannick Casamatta
9fda864835
ci: Add flow for gitlab-ci (#805) 2022-01-27 11:42:10 +01:00
Gianmarco Ottavi
5c0dc1971f
Fixed issue counter in order to leverage the full scoreboad length (#802) 
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
 2022-01-24 19:48:17 +01:00
André Sintzoff
2714b6695c
Makefile: add missing incdir for VCS (fix #791) (#801) 
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
 2022-01-24 19:47:54 +01:00
Florian Zaruba
fc2967cc63
Fix erroneous division (fixes #421) (#796) 
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2022-01-22 08:48:57 +01:00
Nils Wistoff
497236818f
ariane_xilinx: Fix xbar clock (#799) 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-01-22 08:47:26 +01:00
Gchauvon
966b6b3eb7
Update flists to match commit#791 (#795) 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2022-01-19 09:50:59 +01:00
Michael Rogenmoser
4bdfa69d20
axi and common_cells upgrade (#791) 
* Change questa version reference format

* bump common_cells to v1.23

* Bump axi to v0.31.0, replace axi_node with axi_xbar

* Bump register_interface for axi compatibility

* add prot signals to axi_lite for compatibility
 2022-01-15 11:08:14 +01:00
Andreas Kuster
44a89b9cd4
Add fpga cleanup to make clean target (#789) 2022-01-14 15:00:57 +01:00
André Sintzoff
7b916d7ee3
decoder.sv: Remove unnecessary assignment (#788) 
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
 2022-01-14 15:00:17 +01:00
Nils Wistoff
e748564dd8
wb: Check cacheable region length (#784) 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2022-01-08 08:29:30 +01:00