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c511b21911
This code hits verilator/verilator#5829 due to the use of partial assignments to dcache_rtrn_o in this always block, while reading other bits of the same packed struct elsewhere in the block. The actual effect of this is that with a Verilator simulation, invalidation requests incoming from the coherence network are sometimes ignored breaking AMOs. Moving the assignments to the bits read in the always block into the same always block avoids this issue. --------- Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com> Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> |
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| .. | ||
| hpdcache@04de808969 | ||
| amo_alu.sv | ||
| axi_adapter.sv | ||
| cache_ctrl.sv | ||
| cva6_hpdcache_if_adapter.sv | ||
| cva6_hpdcache_subsystem.sv | ||
| cva6_hpdcache_subsystem_axi_arbiter.sv | ||
| cva6_hpdcache_wrapper.sv | ||
| cva6_icache.sv | ||
| cva6_icache_axi_wrapper.sv | ||
| miss_handler.sv | ||
| std_cache_subsystem.sv | ||
| std_nbdcache.sv | ||
| tag_cmp.sv | ||
| wt_axi_adapter.sv | ||
| wt_cache_subsystem.sv | ||
| wt_dcache.sv | ||
| wt_dcache_ctrl.sv | ||
| wt_dcache_mem.sv | ||
| wt_dcache_missunit.sv | ||
| wt_dcache_wbuffer.sv | ||
| wt_l15_adapter.sv | ||