In commit 92b2d0b ("fix fpga bootrom makefile") we should
have tested $(CC) to be not cc if we where not to set the
standard CC and OBJCOPY files.
This should fix building the bootrom and allow overriding
the CC/OBJCOPY when wanted.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
The prints after the command invocation makes it easier to work
out what went wrong if you get errors in the command, which end
up being done silently.
For testing, it is useful to be able to control where the CC and
OBJCOPY commands are coming from.
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Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Use define to constraint function declaration from DPI-C. This was already done in ariane_tb.sv and rvfi_tracer.sv
This prevent an error with xcelium reporting that functions such as read_elf have multiple definitions
Adds support for Trace Interface or Trace Ingress Port (TIP) on CVA6
TIP is Interface between a RISC-V hart and the trace encoder
It generates information about the instruction retired.
The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically:
Chapter 4.1: Instruction Trace Interface Requirements
Chapter 4.2: Instruction Trace Interface
The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump.
What I have been able to test so far:
Simulation: Executed C binaries and observed the waveform of TIP.
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Co-authored-by: root <darshak.sheladiya@sysgo.com>
Co-authored-by: CHAUVON Guillaume <guillaume.chauvon@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
Add parameter CoproType to select which coprocessor to instantiate when CvxifEn == 1
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
* RVFI Tracer : Update tracer to support interrupts
* Randomize sv_seed by default
* Change pc64 to pc
* Fixes
* cva6.py : add the capability to create a log for sv_seed
* Tracer : keep pc64 64 targets failed
* Fix UVM seed for performance tests
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
This PR is adding the APU design adapted to Altera Agilex7 FPGA.
It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.
The former kind of signal initialization generates compilation errors using VCS to simulate the design due to multiple drivers driving those signals. Since these signals are handled inside the always_ff block, they can just be reset.
This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
