AngelaGonzalezMarino
6e0cf8d730
Altera fpga update ( #2790 )
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Update Altera APU design to support linux in both 32 and 64 bits
* Move JTAG UART inside peripherals to properly connect the interruput request to PLIC
* Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version
* Update UART read and write operation in bootrom to allow keyboard interrupt
2025-02-25 22:12:55 +01:00
Guillaume Chauvon
be7c8746c6
Add parameter type to define which coprocessor is instantiated on CVXIF ( #2772 )
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Add parameter CoproType to select which coprocessor to instantiate when CvxifEn == 1
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-02-19 08:52:17 +01:00
Jalali
70972dad54
Update rvfi_tracer and cva6.py ( #2684 )
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* RVFI Tracer : Update tracer to support interrupts
* Randomize sv_seed by default
* Change pc64 to pc
* Fixes
* cva6.py : add the capability to create a log for sv_seed
* Tracer : keep pc64 64 targets failed
* Fix UVM seed for performance tests
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Co-authored-by: André Sintzoff <61976467+ASintzoff@users.noreply.github.com>
2025-01-31 13:10:27 +01:00
AngelaGonzalezMarino
eab88770ec
Altera flow support ( #2649 )
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Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
2025-01-07 23:45:49 +01:00
AngelaGonzalezMarino
f7eb9c1e7b
Altera apu agilex7 ( #2647 )
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This PR is adding the APU design adapted to Altera Agilex7 FPGA.
It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.
2024-12-04 15:54:41 +01:00
Yan
25f2f3190d
Fix $fatal system task incorrect usage ( #2619 )
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To fix #2618
2024-11-20 22:22:50 +01:00
Riccardo Tedeschi
01845dd76b
Initialize mock_uart signals on reset ( #2580 )
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The former kind of signal initialization generates compilation errors using VCS to simulate the design due to multiple drivers driving those signals. Since these signals are handled inside the always_ff block, they can just be reset.
2024-11-05 17:53:48 +01:00
valentinThomazic
a66efad475
fix jal riscv-arch-test ( #2479 )
2024-08-30 07:13:04 +02:00
JeanRochCoulon
d2889fa174
Display number of cycles at test termination ( #2443 )
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Reported by RVFI_tracer module
2024-08-13 17:12:13 +02:00
Guillaume Chauvon
81671e39fa
Fixes and Update CVXIF non regression tests, regression and TB ( #2424 )
2024-08-01 16:06:24 +02:00
Guillaume Chauvon
8fa590b5c3
CVXIF 1.0.0 ( #2340 )
2024-07-12 10:53:18 +02:00
Zbigniew Chamski
48ef515ba0
[Spike Yaml] Integrate Spike Yaml support. ( #2304 )
2024-07-11 08:37:37 +02:00
Moritz Schneider
b6a3aa1b03
Fix non-standard usage of SystemVerilog ( #2336 )
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Strings cannot be initially assigned to an integer without a cast.
2024-07-09 10:39:52 +02:00
Moritz Schneider
246961b3c3
Increase max num PMPs to 64 ( #2279 )
2024-07-04 14:09:37 +02:00
Gregor Haas
c92245b20b
Implement simple uart-based updater for the bootrom ( #2267 )
2024-06-19 11:24:01 +02:00
xiaoweish
c93587b1f9
Update UART submodule to version 0.2.1 and Use SV UART in vcs-testharness ( #2196 )
2024-06-17 09:24:18 +02:00
JeanRochCoulon
e26267b220
[HOT FIX] fix synthesis job ( #2256 )
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Fix read_section_sv type
2024-06-14 08:26:06 +02:00
CoralieAllioux
28e94e5ce3
[Xcelium flow] Clean DPI void function import ( #2222 )
2024-06-12 09:45:33 +02:00
Guillaume Chauvon
a5152b03a5
Add support for cv32a65x dedicated synthesis ( #2178 )
2024-06-04 10:58:09 +02:00
Cyprien Heusse
46e9d5a7fc
32 bits WB cache ( #2170 )
2024-05-30 18:47:39 +02:00
MarioOpenHWGroup
d714d833cb
Bump verif/core-v-verif from f7bda8e to NOTMERGED ( #2044 )
2024-05-30 15:57:58 +02:00
Cyprien Heusse
dd98076a85
tb_wb_dcache updated and adapted for 32-bits ( #2151 )
2024-05-27 10:13:29 +02:00
AngelaGonzalezMarino
ca0cfbcb4e
keep march in bootrom generation without extensions ( #2121 )
2024-05-16 16:27:22 +02:00
MarioOpenHWGroup
8a9d7a832b
Fix RVFI always_ff blocks ( #2053 )
2024-04-18 10:06:34 +02:00
Juan Granja
2182aee119
Update ariane_xilinx.sv ( #1954 )
2024-04-17 11:18:20 +02:00
MarioOpenHWGroup
71ef48804a
[RVFI] Optimize CSRs ( #1999 )
2024-04-15 16:29:07 +02:00
Saute0212
5920e3d125
Add support for Nexys Video board ( #1925 )
2024-04-04 11:13:32 +02:00
JeanRochCoulon
4423feb06a
Rename ZiCondExtEn and FPGA_EN parameters ( #1992 )
2024-04-02 15:37:58 +02:00
MarioOpenHWGroup
08d098bf51
[RVFI] Change CSR implementation ( #1952 )
2024-03-25 12:15:18 +01:00
CoralieAllioux
de2e254cd4
[Xcelium support] Remove void from DPI definition ( #1856 )
2024-03-22 17:07:06 +01:00
MarioOpenHWGroup
62bdf11594
Bump core-v-verif d94f0de and fix questa simulator ( #1915 )
2024-03-21 19:02:41 +01:00
Côme
bd4b57cc64
Parametrization step 3 part 3 (last) ( #1940 )
2024-03-18 16:19:52 +01:00
Côme
4817575de9
Parametrization step 3 part 2 ( #1939 )
2024-03-18 12:06:55 +01:00
Côme
987c645bb7
Parametrization step 3 ( #1935 )
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This is the third step for #1451 . Many values are moved but not all values are moved yet
* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible
2024-03-15 17:21:34 +00:00
Côme
aed4ed7c23
move functions into modules ( #1926 )
2024-03-13 17:46:33 +01:00
Rohan Arshid
c827c3b770
Zcmp extension support ( #1779 )
2024-03-13 11:37:49 +01:00
Côme
83d94bbb69
transform rvfi types into macros ( #1921 )
2024-03-12 17:34:27 +01:00
Côme
32a3cd56ee
Parametrization step 2 ( #1908 )
2024-03-08 22:53:42 +01:00
Yannick Casamatta
bc41a0b7fb
Modify rvfi probes for param change ( #1900 )
2024-03-07 18:34:27 +01:00
Côme
13dfa744d2
Parametrization step 1 ( #1896 )
2024-03-06 17:02:55 +01:00
Yannick Casamatta
1dec79464e
add csr in rvfi ( #1833 )
2024-02-24 00:10:23 +01:00
MarioOpenHWGroup
c7f0eaf0d8
Bump verif/core-v-verif from fd68dfd to c7d2077 ( #1828 )
2024-02-13 14:20:21 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
Michael Platzer
78111aa5eb
config_pkg/csr_regfile: Add PMP entry rst vals & RO option ( #1769 )
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This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
2024-01-17 17:41:38 +01:00
André Sintzoff
3afe870d78
csr_regfile.sv: add RVB field for MISA ( fix #1734 ) ( #1760 )
2024-01-15 14:34:25 +01:00
Guillaume Chauvon
969c91eefa
Check that loaded elf segment does not overlap on last loaded address ( #1755 )
2024-01-11 11:37:00 +01:00
MarioOpenHWGroup
e5a0993ef9
Verilator Tandem Support ( #1702 )
2023-12-12 18:49:49 +01:00
Guillaume Chauvon
cef7e573c4
Set StallRandom I/O to 0 to gain performance on vcs-testharness bench ( #1695 )
2023-12-11 18:53:27 +01:00
AEzzejjari
36c105a50d
Code_coverage: condition RTL with the AxiBurstWriteEn parameter ( #1667 )
2023-12-01 22:59:12 +01:00
