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docs
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📝 Apply memory restructuring changes to BD
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2017-04-21 14:09:13 +02:00 |
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include
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Added decoding of LD/ST instructions
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2017-04-21 12:03:21 +02:00 |
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tb
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Fixes issue #1
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2017-04-19 11:58:23 +02:00 |
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util
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Preliminary instantiation to get run synthesis
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2017-04-13 15:28:09 +02:00 |
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.gitignore
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Doc: Reorganized documentation, generating pages
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2017-04-08 12:31:59 +02:00 |
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.gitlab-ci.yml
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Added scoreboard test to CI
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2017-04-18 20:01:22 +02:00 |
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alu.sv
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Fixes issue #1
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2017-04-19 11:58:23 +02:00 |
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ariane.sv
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✂️ Moved memory management to LSU
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2017-04-21 14:06:38 +02:00 |
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bht.sv
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Added stubs for missing modules
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2017-04-15 18:22:29 +02:00 |
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btb.sv
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Updated README with BTB information
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2017-04-19 20:59:24 +02:00 |
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CHANGELOG
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📝 Add CHANGELOG to gitlab, manually created
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2017-04-21 11:09:30 +02:00 |
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commit_stage.sv
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First test with back to back ALU instructions
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2017-04-17 17:50:41 +02:00 |
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compressed_decoder.sv
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Added IF stage (if stage, prefetcher, fifo)
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2017-04-15 17:59:57 +02:00 |
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CONTRIBUTING.md
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👾 Fixing latches and wrong output assignment
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2017-04-22 12:51:23 +02:00 |
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csr_regfile.sv
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Added stubs for missing modules
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2017-04-15 18:22:29 +02:00 |
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decoder.sv
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Added decoding of LD/ST instructions
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2017-04-21 12:03:21 +02:00 |
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ex_stage.sv
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✂️ Add immediate port and AGU to LSU
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2017-04-21 14:28:44 +02:00 |
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fetch_fifo.sv
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Several bugfixes related to forwarding and if
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2017-04-18 18:39:59 +02:00 |
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id_stage.sv
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Added decoding of LD/ST instructions
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2017-04-21 12:03:21 +02:00 |
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if_stage.sv
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Implemented exception propagation to ex
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2017-04-19 11:53:28 +02:00 |
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issue_read_operands.sv
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Added decoding of LD/ST instructions
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2017-04-21 12:03:21 +02:00 |
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LICENSE
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📝 Add license
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2017-04-21 11:11:40 +02:00 |
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lsu.sv
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✂️ Add immediate port and AGU to LSU
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2017-04-21 14:28:44 +02:00 |
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Makefile
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Added LSU dummy implementation (inc Documentation)
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2017-04-19 17:32:17 +02:00 |
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mkdocs.yml
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Removed hard link to coverage report
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2017-04-09 15:28:55 +02:00 |
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mmu.sv
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Adapted MMU LSU interface signals
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2017-04-19 14:20:00 +02:00 |
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mult.sv
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Added stubs for missing modules
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2017-04-15 18:22:29 +02:00 |
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pcgen.sv
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Added PC generation stage stub
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2017-04-19 20:51:59 +02:00 |
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prefetch_buffer.sv
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Added IF stage (if stage, prefetcher, fifo)
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2017-04-15 17:59:57 +02:00 |
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ptw.sv
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Added stubs for missing modules
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2017-04-15 18:22:29 +02:00 |
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README.md
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📝 Added contribution guide
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2017-04-20 23:06:47 +02:00 |
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regfile.sv
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Preliminary instantiation to get run synthesis
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2017-04-13 15:28:09 +02:00 |
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regfile_ff.sv
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Added initial decoder implementation
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2017-04-15 13:26:33 +02:00 |
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scoreboard.sv
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Fixes issue #7
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2017-04-19 18:30:50 +02:00 |
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tlb.sv
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👾 Fixing latches and wrong output assignment
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2017-04-22 12:51:23 +02:00 |
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wave.do
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First test with back to back ALU instructions
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2017-04-17 17:50:41 +02:00 |
