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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
197 commits 16 branches 13 tags 288 MiB
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Florian Zaruba 6e26afdc2b 🎨 Update header of all src files
2017-05-04 14:54:02 +02:00
docs 🐛 Fix missing pin, wrong fetch data width 2017-05-03 18:29:36 +02:00
include Complete exception wiring and issuing exceptions 2017-05-04 14:38:33 +02:00
src 🎨 Update header of all src files 2017-05-04 14:54:02 +02:00
tb 💚 Fix scoreboard tb with exception WB 2017-05-04 14:46:00 +02:00
uvm-scaffold@2cefe0eae7 💚 Correct Makefile test target 2017-05-03 08:49:54 +02:00
.gitignore 💚 Fixing Scoreboard testbench after #7 2017-04-28 11:57:11 +02:00
.gitlab-ci.yml ✅ Add LSU test, also to CI 2017-05-03 18:50:40 +02:00
.gitmodules Add UVM scaffolding submodule 2017-04-30 18:23:56 +02:00
CHANGELOG 📝 Add CHANGELOG to gitlab, manually created 2017-04-21 11:09:30 +02:00
CONTRIBUTING.md 👾 Fixing latches and wrong output assignment 2017-04-22 12:51:23 +02:00
LICENSE 📝 Add license 2017-04-21 11:11:40 +02:00
Makefile 🎨 Remove debug interface in core def 2017-05-03 17:16:27 +02:00
mkdocs.yml Removed hard link to coverage report 2017-04-09 15:28:55 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00

README.md

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide