docs
|
📝 Add basic information on the testbenches
|
2017-04-28 12:32:26 +02:00 |
include
|
✅ Add empty store queue test
|
2017-04-28 12:58:57 +02:00 |
tb
|
🎨 Reorganizing testbench structures
|
2017-04-30 18:19:27 +02:00 |
util
|
Preliminary instantiation to get run synthesis
|
2017-04-13 15:28:09 +02:00 |
.gitignore
|
💚 Fixing Scoreboard testbench after #7
|
2017-04-28 11:57:11 +02:00 |
.gitlab-ci.yml
|
✅ Add empty store queue test
|
2017-04-28 12:58:57 +02:00 |
alu.sv
|
Fixes issue #1
|
2017-04-19 11:58:23 +02:00 |
ariane.sv
|
Fixes Issue #15
|
2017-04-26 17:04:58 +02:00 |
bht.sv
|
Added stubs for missing modules
|
2017-04-15 18:22:29 +02:00 |
CHANGELOG
|
📝 Add CHANGELOG to gitlab, manually created
|
2017-04-21 11:09:30 +02:00 |
commit_stage.sv
|
Fixes Issue #15
|
2017-04-26 17:04:58 +02:00 |
compressed_decoder.sv
|
🎨 Set correct permissions on src files
|
2017-04-22 12:29:17 +02:00 |
CONTRIBUTING.md
|
👾 Fixing latches and wrong output assignment
|
2017-04-22 12:51:23 +02:00 |
csr_regfile.sv
|
Added stubs for missing modules
|
2017-04-15 18:22:29 +02:00 |
decoder.sv
|
Fixes Issue #15
|
2017-04-26 17:04:58 +02:00 |
ex_stage.sv
|
Implementation start of LSU control
|
2017-04-25 19:59:25 +02:00 |
fetch_fifo.sv
|
🎨 Set correct permissions on src files
|
2017-04-22 12:29:17 +02:00 |
fifo.sv
|
✅ Add memory arbiter test
|
2017-04-27 20:51:52 +02:00 |
id_stage.sv
|
Fixes Issue #15
|
2017-04-26 17:04:58 +02:00 |
if_stage.sv
|
Implemented exception propagation to ex
|
2017-04-19 11:53:28 +02:00 |
issue_read_operands.sv
|
🎨 Set correct permissions on src files
|
2017-04-22 12:29:17 +02:00 |
LICENSE
|
📝 Add license
|
2017-04-21 11:11:40 +02:00 |
lsu.sv
|
✅ Add empty store queue test
|
2017-04-28 12:58:57 +02:00 |
Makefile
|
🎨 Reorganizing testbench structures
|
2017-04-30 18:19:27 +02:00 |
mem_arbiter.sv
|
✅ Add memory arbiter test
|
2017-04-27 20:51:52 +02:00 |
mkdocs.yml
|
Removed hard link to coverage report
|
2017-04-09 15:28:55 +02:00 |
mmu.sv
|
LSU control implement, completely untested
|
2017-04-26 16:53:04 +02:00 |
mult.sv
|
Added stubs for missing modules
|
2017-04-15 18:22:29 +02:00 |
pcgen.sv
|
Added PC generation stage stub
|
2017-04-19 20:51:59 +02:00 |
prefetch_buffer.sv
|
🎨 Set correct permissions on src files
|
2017-04-22 12:29:17 +02:00 |
ptw.sv
|
Add MMU implementation incl PTW and TLBs
|
2017-04-25 13:00:09 +02:00 |
README.md
|
📝 Added contribution guide
|
2017-04-20 23:06:47 +02:00 |
regfile.sv
|
Preliminary instantiation to get run synthesis
|
2017-04-13 15:28:09 +02:00 |
regfile_ff.sv
|
🎨 Set correct permissions on src files
|
2017-04-22 12:29:17 +02:00 |
scoreboard.sv
|
Fixes issue #7
|
2017-04-19 18:30:50 +02:00 |
store_queue.sv
|
✅ Add store queue test, flush missing
|
2017-04-28 18:42:51 +02:00 |
tlb.sv
|
Add MMU implementation incl PTW and TLBs
|
2017-04-25 13:00:09 +02:00 |
wave.do
|
First test with back to back ALU instructions
|
2017-04-17 17:50:41 +02:00 |