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cache_subsystem
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Add option to improve load perf in case OBIVersion==0 or no MMU
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2025-03-05 17:44:35 +01:00 |
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cva6_mmu
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Dcache accesses for AMO and STORE done through OBI bus instead of custom
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2025-03-05 17:44:35 +01:00 |
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cvfpu@3116391bf6
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Cvfpu from vendor to submodule (#2070)
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2024-04-23 14:54:42 +02:00 |
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cvxif_example
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Modify MSUB, NMADD, NMSUB behaviour to differs from other instructions. (#2712)
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2025-01-17 14:12:08 +01:00 |
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frontend
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Improve CC
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2025-03-17 10:48:52 +01:00 |
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include
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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pmp
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id_stage/pmp_entry: Fix formatting (#2705)
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2025-01-15 10:29:18 +01:00 |
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acc_dispatcher.sv
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expand glob port maps (#2585)
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2024-11-07 16:51:46 +01:00 |
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alu.sv
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Adding support for Scalar Crypto Extension (Bitmanip instructions for Cryptography, Zbkb) (#2653)
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2024-12-18 22:35:41 +01:00 |
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amo_buffer.sv
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Set OBI prot field according to standard, 1 for data, 0 for fetch
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2025-03-05 17:44:35 +01:00 |
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ariane_regfile.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_ff.sv
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verible-verilog-format: apply it on core directory (#1540)
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2023-10-18 16:36:00 +02:00 |
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ariane_regfile_fpga.sv
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Altera opt 3 (#2613)
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2024-11-28 14:26:29 +01:00 |
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axi_shim.sv
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Parametrization step 3 part 2 (#1939)
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2024-03-18 12:06:55 +01:00 |
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branch_unit.sv
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Adding support for ZCMT Extension for Code-Size Reduction in CVA6 (#2659)
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2025-01-27 13:23:26 +01:00 |
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commit_stage.sv
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Condition RTL to improve code coverage (#2815)
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2025-03-07 22:00:47 +01:00 |
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compressed_decoder.sv
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Adding support for ZCMT Extension for Code-Size Reduction in CVA6 (#2659)
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2025-01-27 13:23:26 +01:00 |
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controller.sv
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Add RTL configuration RVZifencei
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2025-03-05 17:44:35 +01:00 |
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csr_buffer.sv
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Parametrization step 3 part 3 (last) (#1940)
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2024-03-18 16:19:52 +01:00 |
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csr_regfile.sv
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Improve CC
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2025-03-17 10:48:52 +01:00 |
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cva6.sv
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Add new hierarchy cva6_pipeline (cva6 without L1 caches)
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2025-03-05 17:44:35 +01:00 |
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cva6_accel_first_pass_decoder_stub.sv
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Fix SuperScalar config and add CVA6Cfg to first pass decoder (#2047)
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2024-04-17 16:34:08 +02:00 |
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cva6_fifo_v3.sv
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Spyglass clean up: multiple change to remove Spyglass warnings (#2727)
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2025-01-23 08:32:31 +01:00 |
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cva6_pipeline.sv
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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cva6_rvfi.sv
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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cva6_rvfi_probes.sv
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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cvxif_compressed_if_driver.sv
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Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756)
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2025-02-03 13:40:02 +01:00 |
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cvxif_fu.sv
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Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756)
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2025-02-03 13:40:02 +01:00 |
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cvxif_issue_register_commit_if_driver.sv
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Spyglass clean up: multiple change to remove Spyglass warnings (#2727)
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2025-01-23 08:32:31 +01:00 |
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decoder.sv
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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ex_stage.sv
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Dcache accesses for AMO and STORE done through OBI bus instead of custom
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2025-03-05 17:44:35 +01:00 |
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Flist.cva6
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Add new hierarchy cva6_pipeline (cva6 without L1 caches)
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2025-03-05 17:44:35 +01:00 |
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Flist.cva6_gate
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Add workflow package in uvmt to manage constant like is gatesimu
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2025-03-05 17:44:35 +01:00 |
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fpu_wrap.sv
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Make D independent on xlen (#2005)
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2024-05-12 20:15:50 +02:00 |
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id_stage.sv
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[CV32A6*X] Disable Zifencei across the verification infrastructure. (#2822)
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2025-03-13 06:12:47 +01:00 |
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instr_realign.sv
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Fix: Replace riscv_pkg:VLEN by CVA6Cfg.VLEN
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2024-10-23 18:24:38 +02:00 |
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issue_read_operands.sv
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Improve Code Coverage by conditioning RTL (#2796)
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2025-02-27 12:25:17 +01:00 |
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issue_stage.sv
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Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756)
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2025-02-03 13:40:02 +01:00 |
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load_store_unit.sv
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Add option to improve load perf in case OBIVersion==0 or no MMU
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2025-03-05 17:44:35 +01:00 |
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load_unit.sv
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Set OBI prot field according to standard, 1 for data, 0 for fetch
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2025-03-05 17:44:35 +01:00 |
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lsu_bypass.sv
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Parametrization step 2 (#1908)
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2024-03-08 22:53:42 +01:00 |
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macro_decoder.sv
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Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756)
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2025-02-03 13:40:02 +01:00 |
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mult.sv
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Spyglass clean up: multiple change to remove Spyglass warnings (#2727)
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2025-01-23 08:32:31 +01:00 |
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multiplier.sv
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Spyglass clean up: multiple change to remove Spyglass warnings (#2727)
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2025-01-23 08:32:31 +01:00 |
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perf_counters.sv
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Improve Code Coverage (#2826)
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2025-03-12 23:24:22 +01:00 |
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scoreboard.sv
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Improve Code Coverage (#2826)
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2025-03-12 23:24:22 +01:00 |
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serdiv.sv
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cut dangerous path from flush to issue (#2666)
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2024-12-12 19:10:26 +01:00 |
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store_buffer.sv
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Set OBI prot field according to standard, 1 for data, 0 for fetch
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2025-03-05 17:44:35 +01:00 |
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store_unit.sv
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Add option to improve load perf in case OBIVersion==0 or no MMU
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2025-03-05 17:44:35 +01:00 |
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zcmt_decoder.sv
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Dcache accesses for AMO and STORE done through OBI bus instead of custom
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2025-03-05 17:44:35 +01:00 |
