The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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2017-04-21 10:53:07 +02:00
docs 📝 Added image sources to figure folder 2017-04-21 10:53:07 +02:00
include Make the offset in the BTB variable 2017-04-19 20:52:23 +02:00
tb Fixes issue #1 2017-04-19 11:58:23 +02:00
util Preliminary instantiation to get run synthesis 2017-04-13 15:28:09 +02:00
.gitignore Doc: Reorganized documentation, generating pages 2017-04-08 12:31:59 +02:00
.gitlab-ci.yml Added scoreboard test to CI 2017-04-18 20:01:22 +02:00
alu.sv Fixes issue #1 2017-04-19 11:58:23 +02:00
ariane.sv Instantiated dummy LSU, wired to MMU 2017-04-19 19:17:40 +02:00
bht.sv Added stubs for missing modules 2017-04-15 18:22:29 +02:00
btb.sv Updated README with BTB information 2017-04-19 20:59:24 +02:00
commit_stage.sv First test with back to back ALU instructions 2017-04-17 17:50:41 +02:00
compressed_decoder.sv Added IF stage (if stage, prefetcher, fifo) 2017-04-15 17:59:57 +02:00
CONTRIBUTING.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00
csr_regfile.sv Added stubs for missing modules 2017-04-15 18:22:29 +02:00
decoder.sv Implemented exception propagation to ex 2017-04-19 11:53:28 +02:00
ex_stage.sv Added license headers to files missing one 2017-04-19 19:21:40 +02:00
fetch_fifo.sv Several bugfixes related to forwarding and if 2017-04-18 18:39:59 +02:00
id_stage.sv Fixes issue #7 2017-04-19 18:30:50 +02:00
if_stage.sv Implemented exception propagation to ex 2017-04-19 11:53:28 +02:00
issue_read_operands.sv Fixes issue #7 2017-04-19 18:30:50 +02:00
lsu.sv Added license headers to files missing one 2017-04-19 19:21:40 +02:00
Makefile Added LSU dummy implementation (inc Documentation) 2017-04-19 17:32:17 +02:00
mkdocs.yml Removed hard link to coverage report 2017-04-09 15:28:55 +02:00
mmu.sv Adapted MMU LSU interface signals 2017-04-19 14:20:00 +02:00
mult.sv Added stubs for missing modules 2017-04-15 18:22:29 +02:00
pcgen.sv Added PC generation stage stub 2017-04-19 20:51:59 +02:00
prefetch_buffer.sv Added IF stage (if stage, prefetcher, fifo) 2017-04-15 17:59:57 +02:00
ptw.sv Added stubs for missing modules 2017-04-15 18:22:29 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00
regfile.sv Preliminary instantiation to get run synthesis 2017-04-13 15:28:09 +02:00
regfile_ff.sv Added initial decoder implementation 2017-04-15 13:26:33 +02:00
scoreboard.sv Fixes issue #7 2017-04-19 18:30:50 +02:00
tlb.sv Added stubs for missing modules 2017-04-15 18:22:29 +02:00
wave.do First test with back to back ALU instructions 2017-04-17 17:50:41 +02:00

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide