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Author SHA1 Message Date
Michael Schaffner
045b5707c1 Update google_riscv-dv to google/riscv-dv@6053014 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 605301400555c235564f9336cc5fc220af7e951c

* [style] Break long lines in newly added files (Michael Schaffner)

Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-08 12:32:48 -08:00
Pirmin Vogel
d8e50dcc2c Update google_riscv-dv to google/riscv-dv@ea8dd25 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0

* Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with
  v.1.00 (Pirmin Vogel)
* Added v1.0.0 bitmanip support (Henrik Fegran)
* Remove the pyucis-viewer from requirements.txt (aneels3)
* Update README.md for PyFlow & add pyucis-viewer in requiremen.txt
  (aneels3)
* Fix typo with fs3_sign (aneels3)
* Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3)
* override deepcopy method (aneels3)
* Fix issue with illegal_instr_testi and randselect (aneels3)
* Fixed b_extension_c() issue (shrujal20)
* Fixed get_rand_spf_dpf_value() issue (shrujal20)
* Add support for RV32C coverage (aneels3)
* Add README.md for PyFlow (aneels3)
* Add gen_timeout for PyFlow (aneels3)
* Issue google/riscv-dv#778 fix, change mie behavior in
  setup_mmode_reg (Henrik Fegran)
* Fixed wrong length of I, S, B-type immediates causing wrong sign
  extension for certain instructions (Henrik Fegran)
* Update riscv_compressed_instr.sv (AryamanAg)
* Update var binary of function convert2bin (AryamanAg)
* Improve status reporting (Philipp Wagner)
* update ml/testlist.yaml to get better coverage (Udi Jonnalagadda)
* add m extension covgroup (ishita71)
* Update pygen_src files (aneels3)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:28:50 +01:00
Rupert Swarbrick
8d37af2751 Update google_riscv-dv to google/riscv-dv@59dcd8c 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 59dcd8c813484eb6dcca67e7e36089fe772b9cc8

* Update scripts for Metrics CI regression:  bug fixes, change ISS to
  spike in CI regression (Aimee Sutton)
* Add illegal and load store instruction (aneels3)
* Avoid generating hint instruction when RV32C is turned off
  (google/riscv-dv#787) (taoliug)
* Fix illegal opcode issue in the cov_test (google/riscv-dv#786)
  (taoliug)
* [questa] Remove -access=rwc from vlog command line arguments (Rupert
  Swarbrick)
* [ci] temporarily disable CI flow (Udi Jonnalagadda)
* fix issue with rcs for num_of_harts (aneels3)
* fix multi-hart label issue (aneels3)
* add multi_hart test (ishita71)
* Fix minor issues (aneels3)
* Add riscv_signature_pkg (aneels3)
* add gen_signature_handshake (ishita71)
* Add gen_interrupt_vector_table (aneels3)
* Remove the unnecessary lines (Anil Sharma)
* fix issue with riscv_rand_instr_test (aneels3)
* Add multiprocessing code block (aneels3)

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
 2021-04-06 14:13:39 +01:00
Greg Chadwick
0cb2afffa9 Update google_riscv-dv to google/riscv-dv@0b62525 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0b625258549e733082c12e5dc749f05aefb07d5a

* Add a knob to use rounding mode from the instruction (google/riscv-
  dv#767) (taoliug)
* Add rounding mode support for floating point arithmetic instructions
  (google/riscv-dv#766) (taoliug)
* Fix syntax issue (google/riscv-dv#765) (taoliug)
* Add riscv_amo_instr (aneels3)
* convert string to enum type (ishita71)
* Remove unintended errors in the coverage flow (google/riscv-dv#757)
  (taoliug)
* Fix c_test handling in the YAML testlist (google/riscv-dv#756)
  (taoliug)
* Add support for new Spike trace format (google/riscv-dv#755) (Daniel
  Bates)
* Fix google/riscv-dv#751 for floating point coverage (Weicai Yang)
* Fix issues with implemented TODO's (aneels3)
* fix randomize_gpr (aneels3)
* Add file riscv_b_instr.py (ishita71)
* add std_randomize todo (pvipsyash)
* Add todo for floating_point test (ShraddhaDevaiya)
* Add scripts to integrate with Metrics regression platform (Aimee
  Sutton)

Includes a fix to dv/uvm/core_ibex/sim.py to use `asm_test` rather than
`asm_tests` due to changes in RISCV-DV

Signed-off-by: Greg Chadwick <gac@lowrisc.org>
 2021-02-04 08:37:00 +00:00
Udi Jonnalagadda
c10a050526 Update google_riscv-dv to google/riscv-dv@3da32bb 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3da32bbf6080d3bf252a7f71c5e3a32ea4924e49

* fix location of custom CSR setup (google/riscv-dv#747) (udinator)

Signed-off-by: Udi Jonnalagadda <udij@google.com>
 2020-11-10 11:04:13 -08:00
Udi Jonnalagadda
7aeb2072aa Update google_riscv-dv to google/riscv-dv@3467c37 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3467c3777cb428b2e30b30b7f895a8fd73873d4f

* add VCS compile option for unicode (Udi Jonnalagadda)
* Add missing license header (aneels3)
* [Docs] Fix broken links and typos (db434)
* Add support for RV32D (ishita71)
* Fix google/riscv-dv#733 (aneels3)
* Fix Spike Issue (aneels3)
* add riscv_reg and riscv_privil_reg (pvipsyash)
* fix target issue for foating point (pvipsyash)
* add rv32fc target (pvipsyash)
* add riscv_floating_point_instr (pvipsyash)
* Add defines for floating point instructions (ShraddhaDevaiya)

Signed-off-by: Udi Jonnalagadda <udij@google.com>
 2020-10-30 17:22:46 -07:00
Udi Jonnalagadda
9b656a0a2c Update google_riscv-dv to google/riscv-dv@39797b2 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 39797b2f07784e775149a4f05c90fee2427124e5

* coverage flow updates (Udi Jonnalagadda)
* Update src/riscv_debug_rom_gen.sv (Tom Roberts)
* debug_rom_gen: Fix return address issue (Tom Roberts)
* Add sfence.vma after PTE process (google/riscv-dv#731) (taoliug)
* generate gen_config data in tabular format (aneels3)
* Fix coverage issue for ml target (google/riscv-dv#729) (taoliug)
* Fix index offset constraint conflict (google/riscv-dv#728) (taoliug)
* Fix rcs import and create_instr function (aneels3)
* Fix setup_misa and formatting issue (aneels3)
* Fix SPIKE ISSUE google/riscv-dv#722 (aneels3)
* Fix coverage issue (aneels3)
* fix google/riscv-dv#725 (Udi Jonnalagadda)
* Fix formatting and linting issue (aneels3)
* Add function setup_misa (ShraddhaDevaiya)
* Fix gen_trap_handler_section (aneels3)
* Add constraint (ShraddhaDevaiya)
* Fixed push_gpr_to_kernel def (Saurabh Singh)
* Add ic file to the target dir (aneels3)
* Fix timeout issue (aneels3)
* add mtvec constraint (pvipsyash)
* Fix create_instr issue (aneels3)
* Add function push_gpr_to_kernel (ishitapvips)
* Fix invalid CSR test for RV64GCV target (google/riscv-dv#720)
  (taoliug)
* Fix solve...before... on non-rand variables issue (google/riscv-
  dv#719) (taoliug)
* Add rv32c instructions (aneels3)
* Modify riscv_instr class fields (aneels3)
* Fix import issue (aneels3)
* Significantly improves performance of pyflow functional coverage
  (through changing the way that covergroups are instantiated & data
  are sampled) (Hodjat Asghari Esfeden)
* fix jumps to `test_done` and `init_[m/s/u]_mode` (google/riscv-
  dv#710) (udinator)
* Fix multi-harts program generation with PMP enabled (google/riscv-
  dv#716) (taoliug)
* Fix google/riscv-dv#681 (google/riscv-dv#715) (taoliug)
* Add initial support for rv32imc (aneels3)
* resolve conflicts (aneels3)
* add rv32imc core setting (pvipsyash)
* changes for core settings (pvipsyash)
* add riscv_compressed_instr (aneels3)
* Convert code to be PEP8 compliant (Hodjat Asghari Esfeden)
* Add riscv_data_page_gen (aneels3)
* Integrates functional coverage side of pyflow into cov.py
  (google/riscv-dv#708) (Hodjat Asghari Esfeden)
* Workaround of the SV compilation problem caused by assigning the
  const array variable with the empty concatenation. (google/riscv-
  dv#704) (Dariusz Stachańczyk)
* Add rv32m and rv32c instr defines (ShraddhaDevaiya)
* Fix logging issue along with other minor fixes (Hodjat Asghari
  Esfeden)
* Add push_stack and pop_stack instr. (ShraddhaDevaiya)
* Fix minor issues (aneels3)
* Add a target for RV32IMC with SV32 address translation
  (google/riscv-dv#699) (taoliug)
* Fixes a minot import issue (Hodjat Asghari Esfeden)
* Fix LR/SC sequence issue (google/riscv-dv#698) (taoliug)
* fix ebreak generation bug (google/riscv-dv#689) (udinator)
* Update vector extension to v0.9 (google/riscv-dv#697) (taoliug)
* Fixes a few issues in riscv_asm_program_gen and
  riscv_instr_gen_config (Hodjat Asghari Esfeden)
* fix iterate over args dict (pvipsyash)
* fix parse_args (pvipsyash)
* fix cmdline argparse for directed stream (pvipsyash)
* [pygen/riscv_instr_stream] Fix ebreak generation (Udi Jonnalagadda)
* Fix flake8 related formatting (aneels3)
* Add jal instr (aneels3)
* Fixes for same rd for main instructions (Saurabh Singh)
* Fixes to resolve label issue for directed class (Saurabh Singh)
* Add constraint on jump_start (ShraddhaDevaiya)
* Add Constraint for jump instructions. (ShraddhaDevaiya)
* fix minor issue in directed_lib (pvipsyash)
* Add riscv_jal_instr to directed_lib (pvipsyash)
* Fix forward branch label compilation error (aneels3)

Signed-off-by: Udi Jonnalagadda <udij@google.com>
 2020-10-23 17:00:38 -07:00
Philipp Wagner
f53ee9b09f Update google_riscv-dv to google/riscv-dv@2e52518 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 2e5251846efb5fa42882a2b6b571ef8693e8cd60

* Remove f strings for Python 3.5-compatibility (Philipp Wagner)
* Fix start-end pair mismatch in asm file (aneels3)
* Fix AMO instruction constraint issue (google/riscv-dv#682) (taoliug)
* - Adds support for the coverage report visualization (pyucis-viewer)
  - Adds CSR, opcode, rv32i_misc, and mepc_alignment covergroups
  (Hodjat Asghari Esfeden)
* fix Todo of directed_lib (aneels3)
* Added avail_regs_c constraint (ShraddhaDevaiya)
* Fix factory method implementation (aneels3)
* Add directed instr (aneels3)
* fix label issue (aneels3)
* fix randomization issue (aneels3)
* Fix typo (aneels3)
* add riscv_pseudo_instr (aneels3)
* add value_plusargs functionality (pvipsyash)
* add riscv_utils and fix minor issues (aneels3)
* modify for directed scenario (pvipsyash)
* Fix a minor issue with the instruction PC (Hodjat Asghari Esfeden)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>
 2020-08-20 18:09:11 +01:00
Udi
16ed993486 Update google_riscv-dv to google/riscv-dv@17d7984 
Vendor in some updates to PMP test generation.

Update code from upstream repository https://github.com/google/riscv-
dv to revision 17d79847e376a591cb3dcaae7601c98b0e70e8ac

* Update pygen/pygen_src/isa/riscv_cov_instr.py (Hodjat Asghari
  Esfeden)
* Minor issues fixed in the functional coverage flow (Hodjat Asghari
  Esfeden)
* fix pmp offset constraint (Udi Jonnalagadda)
* Fix minor issues (aneels3)
* - Adds riscv_instr_cover_group file with a few covergroups -
  Confirms riscv_instr_cov_test script is up and running fine -
  Initializes the registers to 0 during their first gpr_state access
  (for ovpsim output log) (Hodjat Asghari Esfeden)
* update directed pmp sequence constraint (Udi Jonnalagadda)
* remove unreachable if...else statement (Udi Jonnalagadda)
* update post_process() (aneels3)
* add ecall_handler (aneels3)
* Fix post_process() issue (aneels3)
* Fix typo in post_process (aneels3)
* Completed riscv_cov_instr class (decoupled from riscv_instr_cov_test
  file) Added private _riscv_cov_instr module to manually retrieve
  format/category/group/imm_t based on the name of the instruction
  (Hodjat Asghari Esfeden)
* add post_process() (aneels3)

Signed-off-by: Udi <udij@google.com>
 2020-08-17 11:53:34 -07:00
Udi
3ddc92a0fa Update google_riscv-dv to google/riscv-dv@61755c0 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 61755c001bec0433fb69458f74d95476d2101cf3

* Adds new PMP directed sequence. (Udi Jonnalagadda)
* Fix typo (aneels3)
* Add gpr_c constraint (aneels3)
* Corrections of a code formatting. (Dariusz Stachanczyk)
* Modify asm, config and pkg files. (aneels3)
* fix riscv_privil_reg compile error (google/riscv-dv#666) (udinator)
* Added methods to the coverage test file (Hodjat Asghari Esfeden)
* Constraints should contain only intergral types - fix added for a
  string variable used in nfields_c constraint. (Dariusz Stachanczyk)
* Minor fixes on coverage test (Hodjat Asghari Esfeden)
* fix pmpcfg csr definitions (Udi Jonnalagadda)
* Pygen: minor fix (danghai)
* Pre_sampling extension (Hodjat Asghari Esfeden)
* Fix opcode in b_extension_c constraint (google/riscv-dv#659)
  (udinator)
* Add vector AMO instruction support (google/riscv-dv#658) (taoliug)
* Terminate when it cannot insert instruction (danghai)
* Riscv_instr_cov added, riscv_instr_cov_test extended, comment
  applied (except for csv_dir) (Hodjat Asghari Esfeden)
* Fix Indentation (aneels3)
* fix imm constraint issue (aneels3)
* fix typo in extend_imm() (aneels3)
* Hodjat (Hodjat Asghari Esfeden)

Signed-off-by: Udi <udij@google.com>
 2020-08-05 01:18:03 -07:00
Udi
216ba1a42d Update google_riscv-dv to google/riscv-dv@3cf691d 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3cf691dcb96f2cd72250690216b60f2b0c0ac804

* remove hardcoded CSR names (Udi Jonnalagadda)
* initial custom CSR support (Udi Jonnalagadda)
* Add support for segmented load/store instructions (google/riscv-
  dv#656) (taoliug)
* fix post_randomize issue (aneels3)
* add MAX_LMUL to rv32i config (google/riscv-dv#649) (udinator)
* Ignore log and asm file (aneels3)
* Add Command Line Support (aneels3)
* support for command-line arguments (pvipsyash)
* Reorder import statements (aneels3)
* Modified function randomize_gpr in instr_stream file
  (ShraddhaDevaiya)
* Updated riscv_instr_sequence file and modified other python files to
  get main block in asm file. (ShraddhaDevaiya)
* Modify get_rand_instr() (aneels3)
* added uvm_glob_to_re in uvm_re_match (Dawid Zimonczyk)
* Aldec Riviera-PRO compiler command line arguments modified.
  (google/riscv-dv#638) (Dariusz Stachańczyk)
* allow coverage compilation to be run on LSF (google/riscv-dv#637)
  (udinator)
* Add CHIPS Alliance work group information to the README
  (google/riscv-dv#633) (taoliug)
* Add indexed/strided vector load/store instrution stream
  (google/riscv-dv#632) (taoliug)
* Add constraint for mtvec alignment in vectored interrupt mode
  (google/riscv-dv#631) (taoliug)
* Add bitstring requirement to pygen/experimental README
  (google/riscv-dv#630) (taoliug)
* Add unsupported load/store instruction filtering (google/riscv-
  dv#629) (taoliug)
* Add different methods to initialize the vregs (google/riscv-dv#627)
  (Josep Sans)
* Support a vetor instruction only mode (google/riscv-dv#626)
  (taoliug)
* Add riscv_instr_stream.py file (aneels3)
* Importing PyVSC module (google/riscv-dv#625) (Hodjat Asghari
  Esfeden)
* update pygen_src files (google/riscv-dv#612) (BharathNR1030)
* Fix typo (google/riscv-dv#624) (taoliug)
* Fix B-ext instruction generation issue (google/riscv-dv#620)
  (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-07-24 00:09:07 -07:00
Udi
e8a71c8ac8 Update google_riscv-dv to google/riscv-dv@6cf6b4f 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6cf6b4f389272d8ff5e2b397af43ac6c0dfba2e2

* Update init value for floating point reg (google/riscv-dv#615)
  (weicaiyang)
* temporarily comment out 4 vector instructions to re-enable coverage
  flow (google/riscv-dv#616) (udinator)
* Fix vector load/store instruction encoding (google/riscv-dv#614)
  (taoliug)
* Add user_init.s to allow custom initialization routine
  (google/riscv-dv#613) (taoliug)
* Fix vector extension config register initialization (google/riscv-
  dv#610) (taoliug)
* Add floating point coverage part2 (google/riscv-dv#600) (weicaiyang)
* Add MAX LMUL configure (google/riscv-dv#609) (taoliug)
* Fix vector unit strided load/store instruction stream name
  (google/riscv-dv#608) (taoliug)
* Update pygen source files (google/riscv-dv#602) (ANIL SHARMA)
* Add vector strided load/store test (google/riscv-dv#601) (taoliug)
* make <main> 4-byte aligned when enabling PMP (google/riscv-dv#596)
  (udinator)
* Fix ius compilation issue (google/riscv-dv#599) (taoliug)
* Integrate Andes's vector extension work to upstream (google/riscv-
  dv#598) (taoliug)
* Fix kernal setcion  PTE setting issue (google/riscv-dv#594)
  (taoliug)
* Add flake8 check for pygen (google/riscv-dv#589) (Hai Hoang Dang)
* Fix MPRV setting issue, it's causing problem for exception handling
  with virtual address translation on (google/riscv-dv#593) (taoliug)
* Fix VSETVL generation issue (google/riscv-dv#591) (taoliug)
* Fix jump instruction stream label issue (google/riscv-dv#590)
  (taoliug)
* Add pygen_src files (aneels3)

Signed-off-by: Udi <udij@google.com>
 2020-06-18 11:05:30 -07:00
Udi
f4366264e4 Update google_riscv-dv to google/riscv-dv@1ad73cc 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 1ad73cc43f8f84d93d49040f8b2928e74efdd854

* Fixes for ML tests (Udi Jonnalagadda)
* Add missing default case to pmp_config (google/riscv-dv#583)
  (udinator)
* various PMP exception handler fixes (google/riscv-dv#581) (udinator)
* convert handshake doc to rst format (google/riscv-dv#580) (udinator)
* Update coverage (google/riscv-dv#584) (weicaiyang)

Signed-off-by: Udi <udij@google.com>
 2020-06-01 08:48:10 -07:00
Udi
ec42eb4409 Update google_riscv-dv to google/riscv-dv@7b38e54 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 7b38e54c5e833f147edc03717b3fd711be923026

* add cmdline configuration of mstatus.mprv (Udi Jonnalagadda)
* Add Xcelium support (google/riscv-dv#579) (Tudor Timi)

Signed-off-by: Udi <udij@google.com>
 2020-05-21 08:28:58 -07:00
Rupert Swarbrick
f767214d88 Update google_riscv-dv to google/riscv-dv@e6a63ff 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e6a63ff19ddf162a89379f9e03f76345c3558ecc

* Restructure coverage (google/riscv-dv#569) (weicaiyang)
* Add --seed_start argument and tidy up seed handling (google/riscv-
  dv#570) (Rupert Swarbrick)
*  Move `sext.b/h` bitmanip instructions to ZB_TMP (google/riscv-
  dv#573) (weicaiyang)
* PR to minor fix for running riscv_asm_program_gen.py (google/riscv-
  dv#571) (Hai Hoang Dang)
* Quickly fix broken link (google/riscv-dv#568) (weicaiyang)

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
 2020-05-19 09:40:26 +01:00
Udi
4814b6776f Update google_riscv-dv to google/riscv-dv@162ea73 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 162ea7312d21ac0b8ae73669fb68bf284b68f851

* Add experimental python based generator (google/riscv-dv#567)
  (taoliug)
* Check return code for ovpsim (google/riscv-dv#566) (taoliug)
* fix bug in PMP handler routine (google/riscv-dv#562) (udinator)

Signed-off-by: Udi <udij@google.com>
 2020-05-11 13:35:21 -07:00
Udi
e1ec5b63f8 Update google_riscv-dv to google/riscv-dv@ace2805 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ace2805b63100f46c3dcd02b4fcf6a7184582110

* Fix vector instruction randomization (google/riscv-dv#560) (taoliug)
* Change generate_instr_stream to a virtual function (google/riscv-
  dv#559) (taoliug)
* fix bug with compressed ebreak generation (google/riscv-dv#557)
  (udinator)
* update PMP exception handlers to 'fix' config CSRs (google/riscv-
  dv#546) (udinator)
* Add bitmanip doc (google/riscv-dv#555) (weicaiyang)
* specify physical pmp addresses from cmdline (Udi Jonnalagadda)
* Fix branch hit coverage issue (google/riscv-dv#551) (taoliug)
* B extension coverage part2 (google/riscv-dv#548) (weicaiyang)
* B extension coverage part1 (google/riscv-dv#542) (weicaiyang)
* Fix typo in riscv_instr_test_lib (google/riscv-dv#545) (ANIL SHARMA)
* Add target rv64imcb (google/riscv-dv#543) (weicaiyang)

Signed-off-by: Udi <udij@google.com>
 2020-05-07 01:23:20 -07:00
Udi
2be109ecca Update google_riscv-dv to google/riscv-dv@42264b7 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 42264b7782a10848935e995063c212893820e561

* fix pmp generation in bare program mode (Udi Jonnalagadda)
* Use literal instead array concatenation (Daniel Mlynek)
* fix access rights (Daniel Mlynek)
* fix in WA fo Aldec Riviera rand cannot be defined in packed struct
  (Daniel Mlynek)
* Fix ius compile error (Weicai Yang)
* fix pmp randomization to adhere to max offset (Udi Jonnalagadda)
* Add options to enable bitmanip by group (google/riscv-dv#532)
  (weicaiyang)
* [pmp] Relative addressing scheme to configure pmpaddr (google/riscv-
  dv#534) (udinator)
* redunant variable ALDEC_PATH removed (danielmlynek)
* riviera 2020.04 beta initial support (danielmlynek)
* Removed  system function call from the gen_section() function
  arguments list. (google/riscv-dv#531) (Dariusz Stachańczyk)
* Dynamic arrays declared as parameter changed to const variables.
  (google/riscv-dv#530) (danielmlynek)
* enhance pmp configuration to make safe region configurable (Udi
  Jonnalagadda)
* Fix a typo in riscvOVPsim (google/riscv-dv#529) (weicaiyang)

Signed-off-by: Udi <udij@google.com>
 2020-04-17 17:06:42 -07:00
udinator
dbbb98f433
Update google_riscv-dv to google/riscv-dv@7675315 (#733) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 76753158d940fffc53fbb92942ae5d1d768a7cdc

* configurable mtvec alignment (google/riscv-dv#527) (udinator)
* Update b-extention (google/riscv-dv#526) (weicaiyang)

Signed-off-by: Udi <udij@google.com>
 2020-03-25 23:56:30 -07:00
udinator
2c198383a3
Update google_riscv-dv to google/riscv-dv@5baf82a (#723) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 5baf82a24347dae3cb71c8ab66a66494666d2291

* Fix illegal func3/func7 instruction generation for B-extension
  (google/riscv-dv#525) (taoliug)
* more tightly constrain pmpaddr values (google/riscv-dv#524)
  (udinator)
* Update style check (Weicai Yang)
* Bump verible (Tomasz Gorochowik)
* Add target for B-extension (google/riscv-dv#521) (taoliug)
* [cov] tag coverage database directories with <test_id> (Udi
  Jonnalagadda)
* Add bit manipulation (google/riscv-dv#518) (weicaiyang)
* Don't change input file in spike_log_to_trace_csv.py (google/riscv-
  dv#504) (Rupert Swarbrick)
* Fix ius constraint solver failure (google/riscv-dv#515) (taoliug)
* Fix AMO sequence address generation issue (google/riscv-dv#514)
  (taoliug)
* Remove alignment constraint (google/riscv-dv#513) (taoliug)
* Add section for each data region (google/riscv-dv#512) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-03-23 13:33:38 -07:00
udinator
73c940a05c
Update google_riscv-dv to google/riscv-dv@3f584ad (#676) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 3f584adef07b7f04edda8a6ba1dfc01a14df5d98

* update ebreak generation for ML test (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2020-03-09 18:55:17 -07:00
udinator
19173290e0
Update google_riscv-dv to google/riscv-dv@6344e95 (#673) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6344e951fef22b383551a85365ebb7d6aa74eb34

* fix incorrect initialization routine (Udi Jonnalagadda)
* Add coverage for single precision floating (Part 1) (google/riscv-
  dv#488) (weicaiyang)
* Add load/store shared memory test (google/riscv-dv#508) (taoliug)
* Fix hart id assignment for load/store instruction stream
  (google/riscv-dv#507) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-03-09 15:53:39 -07:00
taoliug
3d827e1db1
Update google_riscv-dv to google/riscv-dv@4583049 (#660) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4583049cc2b3469ba9dea56b5e2d75809a89d8f3

* Allow running compile command in LSF (google/riscv-dv#506) (taoliug)
* improve documentation of config options (Udi Jonnalagadda)
* Update AMO region and data sections (google/riscv-dv#503) (taoliug)
* Avoid jumping to a sub program of other harts (google/riscv-dv#502)
  (taoliug)
* Use .section for data sections by default (google/riscv-dv#501)
  (taoliug)
* create PMP accessible region for exception handlers and start/end
  sections (Udi Jonnalagadda)
* minor change to signature_addr passed to generator (google/riscv-
  dv#497) (udinator)
* Solve before cconstraints modified (google/riscv-dv#476) (Dariusz
  Stachańczyk)
* Move instruction sections together for multi-harts (google/riscv-
  dv#495) (taoliug)
* add seed capability to CSR test generation (Udi Jonnalagadda)
* fix pmp/shifted_addr compile warning (google/riscv-dv#493)
  (udinator)
* User long jump to switch between different harts (google/riscv-
  dv#491) (taoliug)
* Fix s_region generation (google/riscv-dv#487) (taoliug)
* update rv32imc/riscv_pmp_test testlist options (google/riscv-dv#486)
  (udinator)
* Fix default value of num_of_harts (google/riscv-dv#485) (taoliug)
* Add shared memory region for multi-harts AMO (google/riscv-dv#484)
  (taoliug)
* Add a runtime option num_of_harts (google/riscv-dv#483) (taoliug)
* Add multi-thread support (google/riscv-dv#482) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-03-05 17:21:36 -08:00
udinator
f98cd607af
Update google_riscv-dv to google/riscv-dv@6bd3233 (#617) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6bd323385d454858ea5e50dedd42a563b37931fe

* VCS compile option fix (Udi Jonnalagadda)
* Improve pmp config object - enable cmdline args (Udi Jonnalagadda)
* Fix ovpsim setting (google/riscv-dv#478) (taoliug)
* IUS - enable rand structs in simulation (google/riscv-dv#477)
  (udinator)
* fix macro definition compile issue (Udi Jonnalagadda)
* add ISS command line options (google/riscv-dv#474) (udinator)
* Add style check (Weicai Yang)

Signed-off-by: Udi <udij@google.com>
 2020-02-20 15:07:12 -08:00
udinator
a97b7b7b15
Update google_riscv-dv to google/riscv-dv@6e2bc2e (#589) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 6e2bc2e01fb20799c9eff29a26852eb1917b977a

* fix a missed syntax error in pmp_cfg (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2020-02-06 13:37:00 -08:00
udinator
2be7413ac8
Update google_riscv-dv to google/riscv-dv@e63c542 (#587) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e63c5427b0bf543aebb9c62bba8217065b029a76

* Add pmp configuration object (Udi Jonnalagadda)
* add path for the prebuilt document (google/riscv-dv#469) (taoliug)
* Update document for directed assembly/C test (google/riscv-dv#467)
  (taoliug)
* Fix broken document link (google/riscv-dv#466) (taoliug)
* Add a runtime option to fix stack pointer (google/riscv-dv#465)
  (taoliug)
* Fix LR/SC instruction issue for RV32A (google/riscv-dv#464)
  (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-02-06 11:03:22 -08:00
udinator
230c282c36
Update google_riscv-dv to google/riscv-dv@f7e35d7 (#573) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision f7e35d7939a27ae17b0481eb070e9a36ea335d1f

* remove deprecated code (google/riscv-dv#460) (udinator)
* Integrate directed C test with yaml flow (google/riscv-dv#455) (Hai
  Hoang Dang)
* Qrun is missing -access=wrc option (google/riscv-dv#457) (Hai Hoang
  Dang)

Signed-off-by: Udi <udij@google.com>
 2020-01-28 15:45:41 -08:00
udinator
3d8089c235
Update google_riscv-dv to google/riscv-dv@a655f34 (#564) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision a655f34eb5058da442b38ca010b0d008291c11b5

* Support running C test (google/riscv-dv#453) (Hai Hoang Dang)
* run.py: Do not compare csv file when specified -debug switch
  (google/riscv-dv#451) (Hai Hoang Dang)
* adjust location of nested interrupt mstatus.mie enable
  (google/riscv-dv#444) (udinator)
* Implement storing the commands that would be executed as a script
  (google/riscv-dv#450) (Hai Hoang Dang)
* Move document from README to docs, add HTML preview for the new doc
  (google/riscv-dv#448) (taoliug)
* Use single HTML format (google/riscv-dv#447) (taoliug)
* Update HTML document (google/riscv-dv#446) (taoliug)
* Add framework for custom extensions (google/riscv-dv#442) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-01-23 15:10:14 -08:00
udinator
8ce399dbe6
Update google_riscv-dv to google/riscv-dv@d23da38 (#549) 
* update vendor.hjson to exclude generated pdf file

* Update google_riscv-dv to google/riscv-dv@d23da38

Update code from upstream repository https://github.com/google/riscv-
dv to revision d23da3862f95954e6374aaec787e0fb0c1878a16

* fix matched_list and directed_list size comparisons (Udi
  Jonnalagadda)
* Add run_cmd_output for reporting all debug command lines
  (google/riscv-dv#436) (Hai Hoang Dang)
*  Resolve: missing pass gcc_opts from YAML for GCC compile command
  (google/riscv-dv#435) (Hai Hoang Dang)
* Sphinx: Add generating pdf file (google/riscv-dv#431) (Hai Hoang
  Dang)
* integrate directed asm_tests with yaml flow (Udi Jonnalagadda)
* Fix running cov without arguments (google/riscv-dv#433) (Hai Hoang
  Dang)
* Add setup Travis CI for tracking build docs, and install
  (google/riscv-dv#430) (Hai Hoang Dang)
* Add handling KeyboardInterrupt for run_cmd and run_parallel_cmd
  (google/riscv-dv#424) (Hai Hoang Dang)
* Sphinx: add basic page for structure of the document (google/riscv-
  dv#428) (Hai Hoang Dang)
* README.md: Update the information relating to usage (google/riscv-
  dv#426) (Hai Hoang Dang)
* Add initial Sphinx docs (google/riscv-dv#427) (Hai Hoang Dang)
* Fix typo in the testlist (google/riscv-dv#423) (taoliug)
* Add try-except for handling KeyboardInterrupt (google/riscv-dv#421)
  (Hai Hoang Dang)
* Update information about instruction for running scripts
  (google/riscv-dv#420) (Hai Hoang Dang)
* Add vector permutation, reduction, mask instructions (google/riscv-
  dv#422) (taoliug)
* Python package (google/riscv-dv#419) (Hai Hoang Dang)
* Refactor the code for cov.py (google/riscv-dv#416) (Hai Hoang Dang)
* Update ovpsim config for vector extesion (google/riscv-dv#415)
  (taoliug)
* Fix coverage flow issue (google/riscv-dv#414) (taoliug)
* Add missing license header (google/riscv-dv#412) (taoliug)
* Fix typo in cov_test (google/riscv-dv#410) (taoliug)
* Add vector floating point instructions (google/riscv-dv#409)
  (taoliug)
* Add fixed point arithmetic vector instruction (google/riscv-dv#408)
  (taoliug)
* cov.py: Generate error when it cannot find spike_sim directory
  (google/riscv-dv#407) (Hai Hoang Dang)
* Add vector CSR initialization routine (google/riscv-dv#405)
  (taoliug)
* Create vector extension target, add basic enums (google/riscv-
  dv#404) (taoliug)
* Fix qrun sim warning (google/riscv-dv#402) (taoliug)
* Try fix qrun constraint solver issue (google/riscv-dv#401) (taoliug)
* Fix simulation warning (google/riscv-dv#400) (taoliug)
* run.py: Generate error for gcc compile when it cannot find assembly
  files (google/riscv-dv#398) (Hai Hoang Dang)
* Add numeric corner case test, misc coverage fixes (google/riscv-
  dv#396) (taoliug)
* Switch to new CSV format (google/riscv-dv#395) (taoliug)
* misc fixes for the coverage model (google/riscv-dv#394) (taoliug)
* Fix new CSV coverage flow issue (google/riscv-dv#392) (taoliug)
* Integrate new trace CSV format with coverage flow (google/riscv-
  dv#390) (taoliug)
* Add experimental script for the new CSV format (google/riscv-dv#389)
  (taoliug)
* Support flexible running directed assembly tests (google/riscv-
  dv#386) (Hai Hoang Dang)
* run.py: Enhance passing argument for gen function (google/riscv-
  dv#382) (Hai Hoang Dang)
* Fix qrun issue, take 2 (google/riscv-dv#384) (taoliug)
* Attempt to fix qrun issue (google/riscv-dv#383) (taoliug)
* Fix (google/riscv-dv#381) (taoliug)
* Fix typo (google/riscv-dv#380) (taoliug)
* Fix qrun simulation issue (google/riscv-dv#379) (taoliug)
* Cleaning the output directory by default. Using exist output
  directory (google/riscv-dv#377) (Hai Hoang Dang)
* Fix ius compilation error temporarily (google/riscv-dv#378)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#376) (taoliug)
* Add unaligned jump instruction support (google/riscv-dv#375)
  (taoliug)
* move handcoded asm_test generation into separate output directory
  (Udi Jonnalagadda)
* Ignore return code for ovpsim sim (google/riscv-dv#371) (taoliug)
* Fix mie compare mismatch (google/riscv-dv#370) (taoliug)
* Fix directory/file name for assembly test flow (google/riscv-dv#369)
  (taoliug)
* Fix error in README (google/riscv-dv#368) (taoliug)
* Add sample rv32imc test (google/riscv-dv#367) (taoliug)
* Fix typo (google/riscv-dv#366) (taoliug)
* Support running regression with hand-coded assembly tests
  (google/riscv-dv#365) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2020-01-09 15:04:39 -08:00
udinator
45e7522d1a
Update google_riscv-dv to google/riscv-dv@9ecee87 (#530) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 9ecee87bbc41650ca0f8846de9a277bec2783e18

* fix mmu_stress_test generation failure (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2019-12-18 10:46:36 -08:00
udinator
5c07ced1e3
Update google_riscv-dv to google/riscv-dv@74b8cb6 (#529) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 74b8cb65838f575d6e59e1c80a145d305fbca381

* fix ebreak generation in debug ROM (Udi Jonnalagadda)
* enable nested traps (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2019-12-17 10:54:38 -08:00
udinator
0d6ccbf1f6
Update google_riscv-dv to google/riscv-dv@5b1dd4e (#523) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 5b1dd4e2eb11d49d3275da80953efc0c50f90447

* Add compliance mode to coverage model (google/riscv-dv#361)
  (taoliug)
* Revert " Make assign_operand become a method of class
  RiscvInstructionTraceEntry  (google/riscv-dv#357)" (google/riscv-
  dv#360) (taoliug)
* Fix script issue (google/riscv-dv#358) (taoliug)
*  Make assign_operand become a method of class
  RiscvInstructionTraceEntry  (google/riscv-dv#357) (Hai Hoang Dang)
* Remove unused variable (google/riscv-dv#348) (Hai Hoang Dang)
* Functional coverage improvement (google/riscv-dv#356) (taoliug)
* Fix list access exception thrown when parsing ovpsim illegal
  instruction (Udi Jonnalagadda)
* Add compliance mode and RTL mode to the coverage model
  (google/riscv-dv#354) (taoliug)
* Fix lr/sc sequence (google/riscv-dv#353) (taoliug)
* Fix minor illegal instruction issue (google/riscv-dv#351) (taoliug)
* Migrate to new instruction class (google/riscv-dv#350) (taoliug)
* misc issue fixes (google/riscv-dv#349) (taoliug)
* Update README to add contact info for the collaboration request
  (google/riscv-dv#347) (taoliug)
* Support running specific multiple tests (google/riscv-dv#346) (Hai
  Hoang Dang)
* Fix rv64 coverage model issue (google/riscv-dv#344) (taoliug)
* Fix the link for yaml/base_testlist.yaml (google/riscv-dv#343) (Hai
  Hoang Dang)
* refactor debug ROM generation (Udi Jonnalagadda)
* Add a runtime option to run with experimental features
  (google/riscv-dv#341) (taoliug)
* Fix a few issues with the new instruction class (google/riscv-
  dv#340) (taoliug)
* Improve performance of new experimental instruction class
  (google/riscv-dv#339) (taoliug)
* Fix CSR randomization bug when generating loops (google/riscv-
  dv#337) (udinator)
* Add support coverage flow for qrun, and minor fix for cov.py
  (google/riscv-dv#335) (Hai Hoang Dang)
* [ovpsim] Coding style fixes, fix floating point compare mismatch
  (google/riscv-dv#334) (taoliug)
* Fix ius flow issue (google/riscv-dv#333) (taoliug)
* Fix a few new instruction class issues (google/riscv-dv#332)
  (taoliug)
* Added two includes and starting variables for adding bitmanip
  extension (google/riscv-dv#328) (simond-imperas)
* Integrate experimental instruction class (google/riscv-dv#331)
  (taoliug)
* Minor fixes to run.py (google/riscv-dv#330) (taoliug)
* Run.py: minor refactor the code for compile, and simulate
  (google/riscv-dv#326) (Hai Hoang Dang)
* Add requirements for install dependencies (google/riscv-dv#325) (Hai
  Hoang Dang)
* Adding support qrun simulator (google/riscv-dv#324) (Hai Hoang Dang)
* Add new experimental instruction class (google/riscv-dv#323)
  (taoliug)
* Added command line control of coverage and added hooks for vector
  coverage development (google/riscv-dv#317) (simond-imperas)
* Fix compilation issue (google/riscv-dv#322) (taoliug)

Signed-off-by: Udi <udij@google.com>
 2019-12-16 11:47:53 -08:00
udinator
bb7acbdb7a
Update google_riscv-dv to google/riscv-dv@d691906 (#491) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision d69190682078470bc6d5661d72f873ae9850ae53

* enable CSR randomization only for csr instructions (google/riscv-
  dv#321) (udinator)
* fix csr test script pathname (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2019-11-22 10:17:24 -08:00
udinator
6a582cc11f
Update google_riscv-dv to google/riscv-dv@39ca859 (#486) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 39ca85903eea94350d3a610256307346da407e5b

* Add directed stream to access higher privilege CSRs (google/riscv-
  dv#316) (udinator)
* add config knob for mstatus.tw (Udi Jonnalagadda)
* Fix ovpsim floating point instruction parsing issue (google/riscv-
  dv#313) (taoliug)
* Fix SATP configure issue (google/riscv-dv#312) (taoliug)
* Support import testlist (google/riscv-dv#311) (taoliug)
* Add a rand address load/store test (google/riscv-dv#310) (taoliug)
* Fix ovpsim log parsing issue (google/riscv-dv#309) (taoliug)
* Add a generic approach to check command return value (google/riscv-
  dv#308) (taoliug)
* Fix compile issue (google/riscv-dv#307) (taoliug)
* Basic U-mode support (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
 2019-11-21 11:22:34 -08:00
udinator
6ce8b6ecf2
Update google_riscv-dv to google/riscv-dv@4b333ba (#462) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 4b333ba1ef285ec4508c606efa64610136154a5e

* cg instantion based on supported_isa (google/riscv-dv#303)
  (udinator)
* Fix coverage collection issue, change default target to rv32imc
  (google/riscv-dv#302) (taoliug)
* Integrate whisper(swerv-ISS) (google/riscv-dv#301) (taoliug)
* Fix cov.py, set UVM_VERBOSITY to UVM_HIGH for verbose mode
  (google/riscv-dv#299) (taoliug)
* Fix jalr handling issue for ovpsim (google/riscv-dv#298) (taoliug)
* Add noclean option, change default output directory of coverage
  collection (google/riscv-dv#297) (taoliug)
* Enable using core trace logs for coverage collection (google/riscv-
  dv#291) (udinator)
* Fix isa/mabi setup issue for RV64GC target (google/riscv-dv#296)
  (taoliug)
* fixed line widths (x2) and check error returns for any questa
  simalator (google/riscv-dv#293) (simond-imperas)
* Unknown instruction fix (google/riscv-dv#290) (simond-imperas)
* Fix ovpsim log process issue (google/riscv-dv#289) (udinator)
* adding riscvOVPsim vector instruction trace to csv processing -
  start (3rd Attempt) (google/riscv-dv#288) (simond-imperas)

Signed-off-by: Udi <udij@google.com>
 2019-11-12 14:39:22 -08:00
udinator
498786aef5 Update google_riscv-dv to google/riscv-dv@44bec76 (#447) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44bec7695fd2399166e181fa84b66a608b5f745f

* Re-enable custom OVPsim configuration files (google/riscv-dv#282)
  (udinator)
 2019-11-04 13:41:36 -08:00
udinator
f3f3f3de09
Update google_riscv-dv to google/riscv-dv@cce71d2 (#445) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision cce71d24b56f641d994fbf69b8b50aa3756b9322

* Add handshake documentation (Udi)
* Fix coverage debug mode (google/riscv-dv#281) (taoliug)
* Fix coverage script issue (google/riscv-dv#280) (taoliug)
* code block highlight (google/riscv-dv#279) (taoliug)
* Replace setting directory with a default target (google/riscv-
  dv#278) (taoliug)
* fixed trace handling issues (google/riscv-dv#274) (eroom)
* Allow running the script from other directory (google/riscv-dv#277)
  (taoliug)
* Add dummy writes to status and ie CSRs (Udi)
* Script typo fix (google/riscv-dv#272) (Dan Petrisko)
* Fix misa setup issue (google/riscv-dv#271) (taoliug)
* Enable mie.mtie for timer interrupts (Udi)
* Update illegal system instr generation (Udi)
* Fix duplicate (google/riscv-dv#268) (taoliug)
* Add experimental instruction distribution control (google/riscv-
  dv#267) (taoliug)
* Update README to clarify the flow setup instructions (google/riscv-
  dv#265) (taoliug)
* Remove debug logging (google/riscv-dv#264) (taoliug)
* Fix compressed instruction test setup (google/riscv-dv#263)
  (taoliug)
* adding __init__ in the scripts dir since python3.7 requires that for
  directories to be recognized as modules (google/riscv-dv#252)
  (Jielun Tan)
* Fix riscvOVPsim.ic (google/riscv-dv#261) (taoliug)
* Fix ovpsim sim problem (google/riscv-dv#260) (taoliug)
* Add alternative command options for directed instruction stream
  (google/riscv-dv#254) (taoliug)
* Fix dsim compilation issue (google/riscv-dv#253) (taoliug)
 2019-11-04 10:48:02 -08:00
udinator
c89e431937
Update google_riscv-dv to google/riscv-dv@46ec4bc (#417) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 46ec4bc48bc1eebc5a2bcd48fe4ce4c77105fead

* Incorrect deletion (google/riscv-dv#249) (eroom)
* Updated OVPsim log processing for coverage (google/riscv-dv#248)
  (eroom)
* Improve illegal/hint test coverage (google/riscv-dv#247) (taoliug)
* Coverage model fixes (google/riscv-dv#246) (taoliug)
* Add back-to-back jump instruction test (google/riscv-dv#244)
  (taoliug)
* Functional coverage improvement (google/riscv-dv#243) (taoliug)
* Functional coverage improvement (google/riscv-dv#242) (taoliug)
* Support c.jr,c.jalr, fix coverage sampling issues (google/riscv-
  dv#241) (taoliug)
* allow select a random GPR for JALR op (google/riscv-dv#240)
  (taoliug)
* Fix coverage definition/sampling issue (google/riscv-dv#239)
  (taoliug)
* Testlist clean up, add RV32I target (google/riscv-dv#238) (taoliug)
* Consolidate the coverage collection script (google/riscv-dv#234)
  (taoliug)
* Fixed default values, and trailing blank lines (google/riscv-dv#233)
  (eroom)
* Refine README structure (google/riscv-dv#231) (taoliug)
* Add pre-defined target: RV32IMC, RV64IMC (google/riscv-dv#230)
  (taoliug)
 2019-10-23 10:46:31 -07:00
udinator
b2e36ec345
Update google_riscv-dv to google/riscv-dv@033fccf (#406) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 033fccfbd50f6412e66b448a1d04245d787004bd

* Add more ebreak generation control (google/riscv-dv#229) (udinator)
* Fix timemout, misc update to README (google/riscv-dv#228) (taoliug)
* Fix CSR test setup (Udi)
* Update spike setup instruction for commit log (google/riscv-dv#226)
  (taoliug)
* Fix spike arguments to generate commit log (google/riscv-dv#225)
  (Greg Chadwick)
* Minor README typo (google/riscv-dv#219) (Dan Petrisko)
* Add random FCSR programing, add RV32FC/DC support (google/riscv-
  dv#221) (taoliug)
* Add floating point load/store support (google/riscv-dv#220)
  (taoliug)
* Fix floating point comparison issue (google/riscv-dv#218) (taoliug)
* Add basic support for F/D extension (google/riscv-dv#217) (taoliug)
* Generate the ucdb file inside output directory (google/riscv-dv#215)
  (Hai Hoang Dang)
* cov.py: Allow coverage to run with different simulator
  (google/riscv-dv#214) (Hai Hoang Dang)
 2019-10-16 17:50:23 -07:00
udinator
4a1806f16f
Update google_riscv-dv to google/riscv-dv@ad6fe56 (#385) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ad6fe565a91445cc3ea3e32119360b57af4f19b2

* Workaround for dsim compile issue (google/riscv-dv#211) (taoliug)
* Add a --seed_yaml option to rerun a regression with the same seed of
  a prior regression (google/riscv-dv#210) (taoliug)
* Update questa covearge options (google/riscv-dv#209) (taoliug)
* Fix disable_compressed_instr option (google/riscv-dv#205) (taoliug)
* Fix non-compressed instruction test (google/riscv-dv#203) (taoliug)
* Debug single step functionality and config knobs (Udi)
* Fix no_branch_jump option (google/riscv-dv#200) (taoliug)
* Add more functional covergroup (google/riscv-dv#199) (taoliug)
* Allow randomly reserve GPR for TP/SP, improve functional coverage
  (google/riscv-dv#198) (taoliug)
* Allow running the coverage script with LSF (google/riscv-dv#195)
  (taoliug)
* Add support for disable_compressed_instr (google/riscv-dv#194)
  (taoliug)
* Improve coverage collection performance (google/riscv-dv#193)
  (taoliug)
* Signature_addr_reg constraint update (Udi)
* Add a debug mode for functional coverage (google/riscv-dv#191)
  (taoliug)
* Fix typo in README (google/riscv-dv#189) (taoliug)
* Constrain scratch_reg (google/riscv-dv#188) (udinator)
* Update README for the coverage flow (google/riscv-dv#187) (taoliug)
* Add basic privileged CSR cover group (google/riscv-dv#186) (taoliug)
* Fix cover point definition (google/riscv-dv#185) (taoliug)
* Fix ovpsim log compare issue (google/riscv-dv#183) (udinator)
 2019-10-08 14:22:05 -07:00
udinator
95a82f8be8
Update google_riscv-dv to google/riscv-dv@d341944 (#353) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision d3419444ca2fdb499a204587b2d36c6f5c1e0c44

* Update README (Udi)
* Add knob to enable full CSR randomization, fix mstatus.spp (Udi)
 2019-09-25 18:40:36 -07:00
udinator
83178c69f9
Update google_riscv-dv to google/riscv-dv@e3e1e30 (#349) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e3e1e308cfc3d718aeb94bb3463371979d9a31ae

* Disable full trace in the run script (google/riscv-dv#180) (taoliug)
* Fix spike logging issue (google/riscv-dv#179) (taoliug)
* Add functional coverage for HINT instructions (google/riscv-dv#177)
  (taoliug)
* Add functional coverage for various hazard conditions (google/riscv-
  dv#176) (taoliug)
 2019-09-24 13:55:03 -07:00
udinator
1e8381bfa1 Update google_riscv-dv to google/riscv-dv@4450592 (#347) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44505927a70a6234b996d15f2e51bd1e2632b68e

* Dump performance counters to testbench at EOT (Udi)
* Fix a constraint issue (google/riscv-dv#174) (taoliug)
* Allow split a long test to small batches (google/riscv-dv#173)
  (taoliug)
* Fix ius compile problem (google/riscv-dv#172) (taoliug)
* Add basic functional coverage for RV64IMC (google/riscv-dv#171)
  (taoliug)
* Initial prototype of functional coverage (google/riscv-dv#169)
  (taoliug)
 2019-09-23 18:08:16 -07:00
udinator
2f120d4ade
Update google_riscv-dv to google/riscv-dv@80d4294 (#333) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 80d429475138b4b94d863030246a06980c89889d

* Fix mstatus randomization issue (google/riscv-dv#168) (taoliug)
* Lower the percentage of JAL instruction (google/riscv-dv#167)
  (taoliug)
* Add an option to run a directed assembly test with ISS
  (google/riscv-dv#166) (taoliug)
* Add memory fault handlers (Udi)
 2019-09-18 14:13:03 -07:00
udinator
2c71a26680
Update google_riscv-dv to google/riscv-dv@0d2b5b7 (#321) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0d2b5b7b8b1cdbce74d9e123a427052b12accd7b

* Add user extension support (google/riscv-dv#163) (taoliug)
* Update README (google/riscv-dv#162) (taoliug)
* Fix compilation issue (google/riscv-dv#161) (taoliug)
* Fix compilation issue (google/riscv-dv#160) (taoliug)
* Adding dsim support (google/riscv-dv#159) (taoliug)
* Fix RV64A typo (google/riscv-dv#158) (taoliug)
 2019-09-16 13:43:35 -07:00
udinator
3fcf5a634d
Update google_riscv-dv to google/riscv-dv@c98d89c (#312) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (google/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (google/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (google/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (google/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (google/riscv-dv#148) (taoliug)
* Remove temp files (google/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (google/riscv-dv#144)
  (taoliug)
* Fix typo (google/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (google/riscv-dv#139) (taoliug)
* Remove obsolete sample program (google/riscv-dv#138) (taoliug)
* Update readme (google/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (google/riscv-dv#135) (taoliug)
* Re-organize text and data section (google/riscv-dv#134) (taoliug)
* Refine the bare program mode (google/riscv-dv#133) (taoliug)
* Add a bare program mode (google/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (google/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (google/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (google/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (google/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (google/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix google/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)
 2019-09-13 14:34:56 -07:00
taoliug
6a88d1ed03
Update google_riscv-dv to 102791d (#266) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 102791dbb7eb992d3bc22336d2e4e5f0d688e761

* Merge pull request #104 from google/flow (taoliug)
* Remove debug print (Tao Liu)
* Merge pull request #103 from google/flow (taoliug)
* Improve randomization performance (Tao Liu)
* Merge pull request #102 from udinator/debug (taoliug)
* Prevent x0 from being used as load adress register (Udi)
 2019-08-27 11:23:31 -07:00
udinator
ce8be4f2fd
Update google_riscv-dv to google/riscv-dv@faddfa4 (#263) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision faddfa49f456f3f8ef8c4231865994b7b13aa96d

* Obsolete test clean up (Tao Liu)
* Remove the old flow (Tao Liu)
* minor fix, update README for A extension support (Tao Liu)
* Add basic atomic instruction test (Tao Liu)
* Add RV32A/RV64A instructions (google/riscv-dv#95) (Tao Liu)
* Fix the missing GPR save operations for exception handling (Tao Liu)
* Generate handshake sequence to communicate with testbench (Udi)
* Fix compare error (Tao Liu)
* Fix compare error (Tao Liu)
* Initial signature enum for handshake protocol (Udi)
 2019-08-26 11:41:37 -07:00
taoliug
e2b9c17c0b
Update google_riscv-dv to e81acc9 (#257) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e81acc9ab4f692ff205a207c2dc3d9f2b0284d39

* Merge pull request #89 from google/dev (taoliug)
* Fix mtvec alignement (Tao Liu)
 2019-08-21 18:22:58 -07:00
taoliug
a752277247
Update google_riscv-dv to 73274f2 (#254) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 73274f227000f1316cb201a8503aad437e427948

* Merge pull request #88 from google/dev (taoliug)
* Fix spike log processing issue (Tao Liu)
* Merge pull request #87 from google/dev (udinator)
* Add vectored interrupt support (Tao Liu)
* Merge pull request #85 from udinator/debug (udinator)
* Add debug sub-programs, and extra options to generator (Udi)
* Merge pull request #84 from imphil/fix-apache-urls (taoliug)
* Fix license URLs in comments (Philipp Wagner)
 2019-08-21 17:14:15 -07:00