This sets up Azure Pipelines to run the following two tasks:
- Run Verilator lint on the SystemVerilog code.
- Run the RISC-V compliance test suite for RV32IMC
This commit clarifies why CSR-related pipeline flushes are needed
(e.g. when enabling interrupts), only introduces them when doing the
critical modifications (write/set bits in `mstatus` and `mie` CSRs
for enabling interrupts, reads and clears are uncritical for these
CSRs), and makes sure the controller is actually able to start
handling interrupts while doing a CSR-related pipeline flush.
This resolveslowrisc/ibex#6.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 07599f689a385794cb73932922008bdbe8131d82
* Fix introduced TypeError in run.py (Udi)
Update code from upstream repository https://github.com/google/riscv-
dv to revision e905e9f134e0b7cf7da491218d1a30c75ce8649a
* add pass_val and fail_val into csr test flow for EOT correctness
checking (Udi)
* Support unaligned load/store (Tao Liu)
* refactored test generation logic (Udi)
* refactored test generation logic (Udi)
* Give error when mutually exclusive between -co, and -so argument
(dang hai)
* documentation, and small fixes (Udi)
* no_iss bug (Udi)
* no_iss/no_post_compare optional, CSR read_only is now only specified
at field level granularity (Udi)
* made no_iss optional (Udi)
* rm print (Udi)
* setup_logging call (Udi)
* undo overriding --verbose in run.py, comment cleanup in csr gen
script (Udi)
* missed verbose arguments (Udi)
* verbose arg (Udi)
* updated csr description, integrated csr test into flow (Udi)
* updated csr description, integrated csr test into flow (Udi)
* Enhance verbose information by logging instead of using print (dang
hai)
* Report date time for output directory (dang hai)
* Add main entry point for run.py (dang hai)
* Separate command line parser by function (dang hai)
* Skip generating S/U mode program for machine mode test (Tao Liu)
* minor update to README.md (Tao Liu)
* Update the README.md to match command reference from --help (Tao
Liu)
* Ignore untrack file from python script (dang hai)
* Make questa work for new YAML based regression flow (dang hai)
* Fix typo in README (Tao Liu)
* Fix README google/riscv-dv#54 (Tao Liu)
* changed formatting of generator option table (Udi)
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
This commit makes the BASE field of the `mtvec` CSR writable to
allow changing the trap-vector base address at runtime without
changing the boot address input. Similar to the boot address,
the trap-vector base address must always be aligned to 256 bytes.
At bootup, the trap-vector base address is initialized to the boot
address.
This commit resolveslowrisc/ibex#118.
Most of this work has been done by @ivanmgribeiro as part of
lowrisc/ibex#193.
* ID stage: make single-cycle instr clear `instr_multicycle_done_q`
Previously, this signal was only cleared when starting the next
multi-cycle instruction.
* ID stage: only eval `instr_multicycle_done_q` for multi-cycle instr
This signal should only be evaluated if the ID/EX stage currently
executes a multi-cycle instruction. Without this commit, the signal
is also evaluated for single-cycle instructions and can for example
cause the register file write enable to not be de-asserted in case of
stalls in the IF stage.
This bug was repored by @udinator. This resolveslowrisc/ibex#216.
This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)
This adds Verilator lint support to our fusesoc core file. A waiver file
is created to waive all well-understood lint warnings. The UNOPTFLAT
warnings are not well understood at the moment, they are waived for now
and further discussion is expected to happen in a GH issue (referenced
in the waiver).
Run with
```
fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core
```
The waiver file support requires edalize >= 0.1.5.
Update code from upstream repository https://github.com/google/riscv-
dv to revision a07e0a726edf0230314c08d31546eecbed23054b
* Merge pull request #53 from google/flow (taoliug)
* Update README file for the new flow (Tao Liu)
* Merge pull request #52 from google/flow (taoliug)
* Add timeout mechanism to the flow (Tao Liu)
* Merge pull request #51 from google/flow (taoliug)
* Simulation flow update (Tao Liu)
* Merge pull request #50 from udinator/master (taoliug)
* added license for csr_template.yaml (Udi)
* Merge pull request #49 from google/dev (taoliug)
* Update log process script (Tao Liu)
* Merge pull request #48 from google/dev (taoliug)
* Fix illegal instruction issue (Tao Liu)
* Merge pull request #47 from google/dev (taoliug)
* Refactor the simulation flow (Tao Liu)
* Merge pull request #45 from danghai/master (taoliug)
* Add .gitignore to remove untracked files (danghai)
* Fix warning from Questa optmize (danghai)
* Add optimize log file for Questa simulator (danghai)
* New YAML based simulation flow (Tao Liu)
* Merge pull request #40 from scottj97/typos-redone (taoliug)
* Fix typos in comments (Scott Johnson)
* Fix typos/grammar in README (Scott Johnson)
* Merge pull request #43 from udinator/master (taoliug)
* use hex format in YAML description (Udi)
* CSR test description (Udi)
* removed run script (Udi)
* Modified CSR test generation code to adhere to style guidelines.
(Udi)
* Merge pull request #41 from vandanaprabhu/questa (taoliug)
* CSR Generation Script and YAML template (Udi)
* Prevent Xcelium from attempting to run a simulation during the
compile step (Scott Johnson)
* Document support for Questa (Scott Johnson)
* Fix simulation-time warnings from Mentor Questa (Scott Johnson)
* Fix compile warnings from Mentor Questa (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Fix warning from Questa compiler (Scott Johnson)
* Adding support for using the Questa simulator (Vandana Prabhu)
* Pass proper seed to Cadence Xcelium simulator (Scott Johnson)
* Convert compile commands to functions instead of variables (Scott
Johnson)
