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Author	SHA1	Message	Date
Sven Stucki	45f23be416	Even more compressed instructions	2015-07-16 17:35:49 +02:00
Sven Stucki	4289008afe	Added 6 more compressed instructions	2015-07-16 01:46:29 +02:00
Sven Stucki	a1430b3394	Fixed typo/error in ex stage from last commit	2015-07-14 02:05:13 +02:00
Sven Stucki	7a34cde770	Removed flag from signal and handling from core (still in ALU)	2015-07-14 01:53:10 +02:00
Sven Stucki	0d59ca91d9	More compressed instructions and fixes for existing ones	2015-07-10 12:14:02 +02:00
Sven Stucki	5c93a289ea	Fixed warning in id_stage	2015-07-10 12:13:38 +02:00
Sven Stucki	274901090c	Added default case to RISCV main controller, fixed indentation	2015-07-10 12:10:17 +02:00
Sven Stucki	ce7f33aee8	Improved tracer output for loads	2015-07-10 12:09:06 +02:00
Sven Stucki	f11858a8d8	Major RiscV update, now supports compressed instructions (partially, work-in-progress until full standard is released)	2015-06-12 19:26:16 +02:00
Sven Stucki	aa1821ba2d	Fixed inferred latches in RV	2015-06-05 12:23:35 +02:00
Sven Stucki	b9e0bd9cbd	Fixed missing signal declaration in id_stage	2015-06-01 01:14:38 +02:00
Sven Stucki	60a842c81d	Added all RiscV CSR manipulation instructions, major update and cleanup	2015-06-01 01:01:33 +02:00
Sven Stucki	c0c5b5f8a1	RiscV: exception controller and CSR core and synthesis update	2015-05-26 00:08:44 +02:00
Sven Stucki	01caa041c4	Realigned RiscV with Or10n, code cleanup	2015-05-24 23:04:36 +02:00
Sven Stucki	72147fceed	RiscV update with preliminary exception support, added multiplier and all the other things that didn't survive the GIT reorg	2015-05-20 17:55:43 +02:00
Sven Stucki	29012978d7	Fixed bug in branch code, wrong vector size	2015-04-21 13:31:26 +02:00
Sven Stucki	ff712bf367	Improved instruction tracer, added custom instruction for core id	2015-04-20 11:21:02 +02:00
Sven Stucki	43ccb41536	Reimplemented jumps/branches in a more intelligent way; prevent forwarding of x0	2015-04-19 02:34:43 +02:00
Sven Stucki	10d9a75f27	Fixed space/tab mixture and indentation in instr_core_interface	2015-04-16 15:21:03 +02:00
Sven Stucki	af8b208029	Fixed Jumps and Branches (jump target now calculated in ID, up for debate) and some general code cleanups	2015-04-15 18:27:51 +02:00
Sven Stucki	c974349bbc	Fixed indentation in riscv_core (partially), some changes for to fix jumps/branches	2015-04-14 14:38:49 +02:00
Sven Stucki	902badaf3b	Added BRANCH support	2015-04-13 16:08:27 +02:00
Sven Stucki	20b51d01b4	Added instruction tracer to riscv core	2015-04-10 16:03:16 +02:00
Sven Stucki	c9a0ffdc7d	JAL working	2015-04-09 16:09:37 +02:00
Sven Stucki	6d8d6287b4	Moved LSU addr calculation out of ALU into EX stage	2015-04-08 12:59:22 +02:00
Sven Stucki	5d96d3e7a1	Started implementing JAL/JALR target calculation in ALU, improved a few defaults	2015-04-07 18:35:20 +02:00
Sven Stucki	d7e8aba2f9	Fixed JAL/JALR instruction check, added pretty print function for invalid instructions	2015-04-07 18:15:50 +02:00
Sven Stucki	85d2632a38	Additional code cleanup and defines	2015-04-07 17:26:40 +02:00
Sven Stucki	5e4db58f21	Code cleanup in ID stage	2015-04-07 16:40:45 +02:00
Sven Stucki	a960d85c9e	Fixed indentation in controller (1 level = 2 spaces)	2015-04-07 16:39:28 +02:00
Sven Stucki	a3bce7cb91	Added loads to CPU	2015-04-02 10:32:58 +02:00
Sven Stucki	a6d67016ac	Initial RiscV core commit; still in an early stage, but ALU instructions work	2015-04-01 11:11:07 +02:00