This commit replaces an obsolete assertion with one checking that
response valid is received only if the LSU is ready to handle it.
This resolveslowRISC/ibex#421 reported by @udinator.
These operations (ALU_GT, ALU_GTU, ALU_LE, ALU_LEU) are remnants of
of the original OpenRISC design. RISC-V does not have these instructions
and instead implements the operations by reversing operands for ALU_LT,
ALU_LTU, ALU_GE, ALU_GEU.
This resolveslowRISC/ibex#420 reported by @udinator.
When we single step over an instruction that causes an exception DPC
should be set to point to the exception handler (where we would have
gone were we not single stepping).
Fixes#393
When entering debug mode in controller need to ensure ID doesn't get
flushed until the relevant debug state can see the contents of ID and
perform the appropriate actions. ID is flushed at that point.
Also cleaned up some code replication around entering debug mode
(debug_req vs single step look very similar so can use the same code
paths).
Debug register access sets illegal_csr if not in debug mode but CSR
write still went ahead. This modifies the CSR write to ensure that
anything that results in an illegal CSR instruction being signalled will
prevent a CSR write.
- If an error is signalled in the first part of an unaligned
transaction, the second part is issued anyway (to avoid a
timing loop from data_err_i -> data_req_o)
- Previously, the error was signalled and an exception was taken
as soon as the first transaction completed. This commits makes
the core wait until both transactions have completed.
- This prevents strange behaviour caused by the lsu and controller
being out of sync (fixes#374).
This miscompilation is now reported and fixed, mention it in the code to
refer back to it when we can revert back to the old code (which will
take a couple months until we can require a newer Verilator version).
Fixes#372
The ibex_tracer module implements an execution tracer, observing the
execution flow and writing a human-readable execution trace. The trace
information is coming from the RVFI signals, as specified at
https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md.
The existing implementation was tailored for use in ModelSim and other
commercial simulators, and used SystemVerilog features which are not
supported in Verilator or Icarus Verilog, such as classes, queues and
non-standard format specifiers (e.g. the `-` specifier for right-aligned
output). Being unable to see an execution trace when using Verilator
significantly reduced productivity and its usefulness.
This commit refactors the tracer to only use SystemVerilog constructs
which are supported in Verilator. While doing so, multiple improvements
were made for correctness and style.
Major changes:
- Improve compatibility with Verilator. Remove many non-synthesizable
SystemVerilog constructs, such as classes and queues.
Use casez instead of casex for better Verilator support (Verilator
doesn't support X).
- Make the decoded output of the tracer match objdump from binutils
exactly. Doing so is beneficial for two reasons: we can easily
cross-check the decoded output from the tracer against the disassembly
produced by objdump (and we did that), and users don't need to get
used to another slighly different disassembly format.
- A plusarg "+ibex_tracer_file_base=ibex_my_trace" can be used to set a
different basename for the trace log file.
Smaller cleanups:
- Remove decoding of reg-reg loads, which were leftover from a PULP
extension.
- Make better use of the data available on the RVFI. Pass all of RVFI
to the tracer, and use the provided data instead of manually
recreating it, e.g. to get register data or the jump target.
- Rename all "instr" abbreviations to "insn". "insn" is what RVFI uses
(and we cannot change that), so for consistency we now always use this
abbreviation across the file.
All CSR names have been imported from binutils' riscv-opc.h file, available at
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=include/opcode/riscv-opc.h
using this small C program:
#include <stdio.h>
#define STR(s) #s
int main(int argc, char **argv) {
printf("unique case (csr_addr)\n");
#define DECLARE_CSR(name, csraddr) \
printf(" 12'd%d: return \"%s\";\n", csraddr, STR(name));
#include "riscv-opc.h"
printf(" default: return $sformatf(\"0x%%x\", csr_addr);\n");
printf("endcase\n");
return 0;
}
The RISC-V compliance test suite for the RV32 I, M, and C extensions has
been executed and traced. The disassembly of all traces have been
compared against traces produced by objdump to ensure identical output.
This PR is based on work by Rahul Behl <raulbehl@gmail.com> in #280.
Thank you Rahul for providing a great starting point for this work!
When an exception occurs controller goes into the flush state and then
does a pc_set to go the exception handler. So there is no need for the
incoming signals that indicate an exception to factor directly into
pc_set_o. This flops exc_req and illegal_insn to break long timing
paths that were occurring because of this.
Fixes#305
When an instruction that caused an exception occurred the controller
would clear the instr_valid bit but rely on the instruction bits staying
in the ID register so it could still use them in the FLUSH state to
decide what to do. This reworks the control logic slightly so
instr_valid remains asserted when the controller goes into the FLUSH
state so relevant signals can be qualified with the instr_valid bit.
There were no known functional issues caused by the previous behaviour
however this gives a more robust approach.
The syntax of this statement is not correct without the `$fatal()` SV
construct. This causes errors in some tools even if the error condition
is not met.
- Fixes#288
- Add missing grant qualification to stop incorrect address updates
- Make RTL robust to spurious rvalid signalling
- Make sure a request is held until granted
- Remove incorrect assertion
Without this commit, the `nmi_mode` register is continuously cleared and
set again, and the core can never handle the NMI.
This resolveslowRISC/ibex#300 reported by @udinator.
This commit fixes the generation of the exception cause ID for fast
interrupts. Without this commit, the core tries to handle fast
interrupts using the handlers of other interrupts like external,
software, and timer interrupts.
This commit resolveslowRISC/ibex#290 reported by @udinator.
- See issue #265 (partially fixes)
- Remove path from instr_rvalid_i to instr_req_o
- Prefetch buffer unit can now issue up to two outstanding requests
- Structure moved from state machine to request queue
- Change fetch fifo to use an unaligned flag rather than updating
the address each time
- Relates to issue #265
- External signals data_rvalid_i and data_err_i were factored
into the external data_req_o signal
- To improve timing, these signals are decoupled
- The second part of an unaligned transaction will now be issued
even if the first received an error response
- The state machine will service the abandoned requests
- pmp_err_q fixed to only update at specific times
- The RISC-V Debug Spec v.0.13.2 (p.41) mandates that the core
debug CSRs dcsr, dpc, dscratch0 and dscratch1 must not be
accessible if not in debug mode. Fixes#275
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
Executing a DRET instruction outside of debug mode now causes an
illegal instruction exception as mandated by the Debug Spec v0.13.2
p.41.
This resolveslowRISC/ibex#270.
