It is not necessary to do this check in the compressed decoder. If a
compressed instruction in RV32E tries to access any register x16 - x31,
the regular decoder triggers an illegal instruction exception and the
controller writes the actual faulting (compressed) instruction to
`mtval`.
To make the regfile address check in RV32E not triggering false alarms
when accessing reg x16 - x31, the decoder should only set the muxes
for the regfile output when the instruction actually requires the
regfile output.
It is cleaner to explicitly set the `alu_op_x_mux_sel` signals to
`OP_X_REG_X` instead of relying on the default assignment if they
are really needed.
This commit cleans up the LSU and fixes two bugs:
1. If a misalgned transaction creates an error during the first
part of the transaction, the second part is not pushed out and
the transaction is aborted. Previously, the LSU tried to output
also the second part but did not adhere to the defined
protocol.
2. Misaligned operations are again working correctly. Previously,
the generation of the byte enable and the alignment of read
data was broken as these operations rely on the updated
address from the AGU to have the same alignment as the
original address.
This partially resolves#121.
This commit moves logic directly related to the decoder from the ID
stage into the decoder. This logic includes:
- Generation of immediates and decoder-based mux selectors
- Generation of register file addresses
- CSR operand check and manipulation depending on value in `rs1`
- Register file address check for RV32E (still disabled)
The muxes themselves stay in the ID stage as their control signals also
depend also on other, non-decoder-based signals (LSU, EX, WB FSM).
These signals do not need to be generated by the WB FSM inside the ID
stage and be fed back into the decoder. They simply depend on whether
the instruction is new (we execute for the first cycle) or not.
The EX block actually signals when its output is valid, and not when it
is ready to accept new input. The LSU valid signal is not needed inside
the EX block and can thus be fed directly to the ID stage.
This commit makes sure that if any instruction is detected as being
illegal inside the decoder, the decoder does not set the control
signals to let the illegal instruction affect the register file,
LSU, EX, WB, CSRs. Previously, this was only the case for some but
but not all instructions.
Note that this is not sufficient to prevent instructions detected
as illegal elsewhere from affecting the processor state. For example,
when using RV32E, an instruction can be detected to use unavailable
registers outside the decoder in the ID stage. But it is cleaner to
handle all illegal instructions detected in the decoder similarly.
For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.
Interrupts are handled in vectored mode as before.
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
This operation only depends on the LSU detecting a misaligned address.
Previously, the mux control was scattered across ID stage, controller
and decoder. With this commit, all the relevant code for this operation
is moved into the ID stage and also streamlined.
Verilator displays the following lint warnings:
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv💯 Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'RV32E' generates 1 bits.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv:103: Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'RV32M' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv:108: Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'MXL' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_register_file_ff.sv:63: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'waddr_a_i' generates 5 bits.
It's not quite clear (to me) from reading the SV spec if this is a bug
in Verilator lint, or if this is actually a code bug.
Alternative proposal for #92
Performance counters are an optional feature. Disable them by default to
avoid users having them enabled unknowingly and paying the (rather
large) area price for it.
The core handles unaligned instruction fetches by doing two separate
word-aligned instruction fetches. Without this commit, the core can
still output addresses which are not word aligned and relies on the
memory to ignore the LSBs of the address. This is not safe.
The core handles unaligned accesses by doing two separate word-aligned
accesses. Without this commit, the core can still output addresses
which are not word aligned and relies on the memory to ignore the LSBs
of the address. This is not safe.
Without this commit, the performance counters mhpmcounter3(h)-
mhpmcounter31(h) are optimized away during synthesis due to
`X`-values in the address decoder masks. This commit replaces
these masks with offsets and instead masks the input address
before comparison.
To enable the synthesizer optimizing away unused counters,
the masks for these counters are set to zero.
Without this change, the core can continue to write CSRs during multiple
subsequent clock cycles when being stalled. This can corrupt CSR (e.g.
performance counters).
