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1819 commits 21 branches 8 tags 72 MiB
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Author SHA1 Message Date
Andreas Traber
3495998840 Added vectorial comparisons and started decoding the rest of the vectorial operations, still needs testing though 2016-03-02 10:11:48 +01:00
Andreas Traber
4efa86705c Added pv.ball instruction 2016-02-25 14:21:50 +01:00
Andreas Traber
e423b2c197 Added p.extract, p.extractu, p.insert, p.bclr, p.bset instructions 2016-02-25 12:23:24 +01:00
Francesco Conti
f436596e6f fixed src_files.yml 2016-02-18 21:00:38 +01:00
Andreas Traber
cc82192e45 Make sure the prefetcher works with any kind of stalls on data and 
instruction RAM access
 2016-02-19 10:41:55 +01:00
Andreas Traber
f46dbaefad Fix two issues when the core is not getting the grant immediatly after 
sending the request
 2016-02-18 10:16:21 +01:00
Andreas Traber
50ee8b6ef5 Move riscv_tracer to different sub ip in src_files 2016-02-17 18:22:02 +01:00
Francesco Conti
d5a262cf24 fixed src_files.yml 2016-02-17 14:50:03 +01:00
Andreas Traber
9858198ee5 Fix a bug in the LSU by making sure that branches can be finished 
correctly in the EX stage without impacting the WB stage

Also align simchecker and tracer to this
 2016-02-16 19:59:51 +01:00
Andreas Traber
18f5ffcd4a Fix wait_gnt signal for prefetcher if transaction was aborted 2016-02-16 17:24:14 +01:00
Andreas Traber
656c391215 Respect jump done in controller for the eret instruction 2016-02-16 17:21:24 +01:00
Andreas Traber
6b22441367 Fix handling of packed/unpacked structs in the riscv tracer 2016-02-16 17:19:18 +01:00
Francesco Conti
2e7d74c8a6 moved src_files.txt to src_files.yml 2016-02-11 16:41:29 +01:00
Francesco Conti
98a815fbc6 moved src_files.txt to src_files.yml 2016-02-11 16:35:43 +01:00
Francesco Conti
9ecd6d9868 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-02-11 16:14:50 +01:00
Francesco Conti
c894ae0aec added FPGA-friendly register file to src_files.txt 2016-02-11 16:07:09 +01:00
Andreas Traber
a8987b5890 Added a basic description of the pipeline 2016-02-11 15:58:29 +01:00
Andreas Traber
6f3358adfd Clarified hwloops with same endpoint 2016-02-11 14:10:26 +01:00
Andreas Traber
918caba6f3 Update tracer and simchecker to be more verbose 2016-02-11 13:48:28 +01:00
Andreas Traber
8c130d6398 Add README 2016-02-10 17:25:56 +01:00
Andreas Traber
993e254947 Start adding interrupt support to simchecker 2016-02-10 10:24:49 +01:00
Andreas Traber
33987fcc6c Handle boot address correctly 2016-02-09 17:38:41 +01:00
Andreas Traber
c39e27f3ac Allow nested interrupts and save current value of MSTATUS to MESTATUS 
upon entering an interrupt handler
 2016-02-09 09:21:26 +01:00
Andreas Traber
d99c3c9f24 Simchecker now also supports rvc 2016-02-08 13:08:56 +01:00
Andreas Traber
f95e08bf64 Finish sim checker. It passes coremark on pulpino, so relatively mature :-) 2016-02-07 13:21:08 +01:00
Andreas Traber
e7f5ef8336 Prepare for simchecker 2016-02-07 13:21:08 +01:00
Francesco Conti
8720d93a21 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-02-05 12:24:24 +01:00
Andreas Traber
3d768d27ab Fix issues in instruction tracer and align with virtual platform 2016-02-04 16:43:27 +01:00
Francesco Conti
2a9bb089e0 added src_files.txt 2016-02-03 17:27:24 +01:00
Andreas Traber
9f19da8c2f Move to classes for tracer 2016-02-02 17:31:26 +01:00
Andreas Traber
c91e3a621e Add memory transactions to tracer and align better with simulator 2016-02-02 14:49:40 +01:00
Andreas Traber
1938b1c768 Make tracer look nicer 2016-02-01 16:59:16 +01:00
Andreas Traber
9d03afe12c Switch to queue for instruction tracer 2016-02-01 15:46:58 +01:00
Andreas Traber
a8d66afa71 Refactor riscv tracer and put it in own module 2016-02-01 13:27:32 +01:00
Andreas Traber
5e90564929 Make sure the address is kept stable when we are waiting for a gnt 2016-01-23 00:35:01 +01:00
Andreas Traber
53f0dbda25 Fix net declaration 2016-01-21 15:11:32 +01:00
Andreas Traber
531745d656 Update documentation and instruction tracer for new encoding 2016-01-21 14:30:11 +01:00
Andreas Traber
a15f007d46 Change to new encoding from Eric 
This changes the way mac and mul are handled and moves the rs3 register
for mac operations.
When rs3 is not used, the register file port is now silenced
 2016-01-21 13:08:16 +01:00
Andreas Traber
11ffa5630c only jump once even when there are stalls 2015-12-26 13:30:44 +01:00
Andreas Traber
1b98c11e12 Remove mscratch and change the way csr works 2015-12-26 00:15:00 +01:00
Andreas Traber
49532dfa79 More enables on pipeline registers 2015-12-23 16:35:52 +01:00
Andreas Traber
db9e184054 use separate registers for multiplier and do smarter enable in the 
pipeline

This saves up to 20% power compared to the previous solution
 2015-12-23 12:41:19 +01:00
Andreas Traber
7ec2f6410f Add LSU instructions to datasheet 2015-12-23 10:34:13 +01:00
Andreas Traber
981cd4789b Add block diagram to titlepage 2015-12-22 16:30:42 +01:00
Andreas Traber
cfc1a17419 Add the rest of the extended alu operations 2015-12-22 16:13:20 +01:00
Andreas Traber
5a0e624be7 Add description of most alu ext operations 2015-12-22 14:32:46 +01:00
Andreas Traber
e4cbf45209 Add chapters about hardware loops and multiply-accumulate 
Add instruction specification of pulp extensions
 2015-12-22 11:16:47 +01:00
Andreas Traber
dc8144a459 Added more information about debug to documentation 2015-12-21 14:54:37 +01:00
Andreas Traber
e9197db83c Working on the documentation 2015-12-21 13:04:50 +01:00
Andreas Traber
2b8fdcd6d3 Update pc counters, branches taken were wrong 2015-12-16 11:17:37 +01:00