This commit introduces the use of a pydantic model to validate the
data used to define directed tests. 'pydantic' is a python data validation
and settings management library which allows for structured data to be
checked against 'pydantic models'. In this case, we define a 'model' for
how we expect the directed-test yaml to look, including fields and datatypes,
and then validate that the imported file matches this expectation.
In effect, it allows the checking of the data to be seperated from its use.
dv/uvm/core_ibex/scripts/directed_test_schema.py defines the pydantic model,
and provides a function 'import_model()' to check the file-contents and
return a valid dictionary of the structured data.
* First implementation of a directed_test framework, which aims to re-use as much
as possible from the existing riscvdv generation
* Fixed directed test flow to cleanly end the test
* clang-format is off for assembly header files
This commit adds two assertions in `ibex_top` to ensure that the
scramble key is correctly applied to the icache scrambled memory
primitives. Those assertions previously existed in the module that
instantiated Ibex in OpenTitan, but the reference into the generate
loops was problematic for some EDA tools; see lowRISC/opentitan#17155.
Additionally, the assertions previously used the input scramble key
(`scramble_key_i`) even though they tolerated a delay after which the
input scramble key was not necessarily valid anymore (i.e.,
`scramble_key_valid_i` could go low and `scramble_key_i` could take any
value). This mistake has been corrected by sampling the input scramble
key for the assertions when it is valid and using the sampled value in
the comparison of the assertions. This problem surfaced in the DV
environment of Ibex (but not in OpenTitan), where multiple tests
(including `riscv_rand_instr_test`, `riscv_mem_error_test`, and
`riscv_multiple_interrupt_test`) failed; these tests now pass.
Signed-off-by: Andreas Kurth <adk@lowrisc.org>
Starting with setuptools version 66.0.0, legacy package version names
such as 0.23ubuntu1 are no longer supported. Since some of our
Python dependencies use this format, we pin the setuptools version to
the last version before this change. This unblocks CI and gives us time
to upgrade/rebase our dependencies.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Previously, it was possible to glitch data_rvalid_i at the interconnect
level and if the data integrity bits happened to be valid, Ibex would
write the current data_rdata_i into the register file even if it wasn't
doing a load. Since the glitch is inserted at the interconnect level,
both the main and the shadow core are affected equally.
This commit changes the WB stage to only forward the LSU write enable,
which is generated from data_rvalid_i, when Ibex is actually waiting for
an interconnect response for a load instruction. This substantially
narrows down the window for attacks at the interconnect level.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Xprop is a simulation feature that improves the SV semantics when
conditions contain 'X values. Change RTL or DV code to enable more xprop
instrumentation.
This addresses lowRISC/opentitan#16791 and some of
lowRISC/opentitan#16723.
Signed-off-by: Guillermo Maturana <maturana@google.com>
It randomly writes to fields of cpuctrlsts to enable and disable data
independent timing, dummy instruction insertion and the icache. This is
used in riscv_debug_basic_test and riscv_single_interrupt_test to see
interrupts and debug requests when dummy instruction insertion and data
independent timing is enabled.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 68ab8230c52ec66b393c04394aef4d6082ee53b4
* [pmp] Ensure MML PMP configurations don't dominate. (Greg Chadwick)
* [pmp] Add option to constrain addresses to stay in 32-bit space
(Greg Chadwick)
* randomizing mstatus.MIE when priv mode is lower than machine (Saad
Khalid)
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This is used in riscv_pmp_full_random_test as some executions of that
test run very slowly. These are still valuable so the timeout is used to
ensure they don't take too long but still result in a pass.
This helps reduce repetition in the CI yaml in preparation for adding
more directed tests.
This is a very basic script and will be replaced by a more complete
system at a later point.
cov_merge.tcl has been patched so the Ibex regression can pass through
coverage directories via a file. However this breaks dvsim based flows,
in particular the icache coverage merge.
This patch checks to see if the file is provided, if not it uses the
original merge method that's compatible with dvsim.
The new instruction stream randomly chooses a NAPOT PMP region and emits
a store or load which will cross the boundary of that region at either
the top or the bottom.
