The register is redundant to the PLIC in pulpissimo and is never written by the PULP_SDK.
Therefore enable all Interrupts from the beginning to ensure functionality.
This commit adds 32 non-standard, custom, fast interrupts to Ibex. These
interrupts are managed via 3 custom CSRs: `miex`, `mipx` and `mtvecx`.
`mtvecx` is initialized just like `mtvec`. Upon handling such a custom
interrupt, the core uses two signals (ACK + ID) to inform a possible
platform-level interrupt controller accordingly.
The purpose of adding these non-standard interrupts is to have an
interrupt framework compatible with RI5CY/CV32E40P for platforms that can
use the two cores interchangeably (PULP/PULPissmio).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit replaces the generic `prim_clock_gating` cell with the
`cluster_clock_gating` cell used in PULPissimo.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit modifies the encoding of SROI, RORI, SBEXTI, GREVI and GORCI by
forcing Bit 26 to zero to prevent overlapping encodings with FSRI.
The bitmanip draft spec doesn't explicitly state that Bit 26 for those
instructions must be zero. However, those instructions only ever use
log2(XLEN) LSBs of the immediate. This means they don't use Bit 26 in RV32.
Instead, whenever Bit 26 is set, these instructions are instead decoded as
FSRI.
This fixes a bug where .csv.rpt files weren't being generated properly.
OpenSTA was outputting a simple 'Q' or 'D' for start and end path points
where the full instance name was required (which is then fed to yosys to
translate to a human readable name). The issue was in the `timing_report`
proc in syn/tcl/sta_utils.tcl which needed to request the full name of
the start and end points.
The syn README is updated to note which tool versions have been used to
test the flow.
Fixes#1193
Forward a currently unused parameter.
Disable error exit for warnings. Newer Verilator versions will fail if
for example parameters are unused. As this test does not cover
everything, allow those warning to be printed, but not fail the build.
The parameters are not used as the instructions are not yet widely
supported.
Keep definitions so they can be easily activated later.
Tracked in issue lowrisc/ibex#1228
In the past, we did explicitly install pyyaml through PIP to get a
version newer than the one provided in Ubuntu 18.04. Since then we
changed the calling code to not rely on newer pyyaml features and
are thus able to rely on an older version of pyyaml.
The distro-provided version of pyyaml is built with C bindings, which
are significantly faster than the pip-installed version, which uses a
pure Python-implementation of the parser/dumper.
Xcelium 19.03 doesn't support the `->` (binary logical) operator, but
using `|->` (overlapping implication) is equivalent here and supported;
use this operator instead.
Fixes#1213
The GitHub UI shows apparently the name of the template at
https://github.com/lowRISC/ibex/issues/new/choose, which I thought was
just an internal identifier. Use the longer-form version there as well.
Add two issue templates to the GitHub project: one for questions, and
one for reporting bugs. These templates are not mandatory, users can
freely change them, or get a blank issue template instead.
To avoid having too much description/example text in the final issue the
instructions are written in HTML comments (which is not beautiful, but
should do the trick and seen commonly in projects).
These changes correspond to similar changes in the prefetch buffer to
support branch prediction. A registered version of fill_ext_done was
required to prevent a combinational loop from branch_i in to valid_o
out.
Multiplexing priorities for fifo_addr have been swapped to match
fetch_addr_d in the same module and all similar multiplexing in the
icache (prioritize incoming branch_i over branch_mispredict_i). Note
however that it is not expected that these conditions will actually
occur together, and an assertion has been added to check that.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Remove the SpeculativeRequest parameter, and replace it with a
policy. If the cache is disabled, make the request on the basis that we
definitely won't hit in the cache and so should make the bus request
asap.
Stop fill buffers from fetching complete cache lines when the cache is
disabled. When the core branches into the middle of a line, the lower
words would normally be fetched to complete the line. This is
unnecessary when the cache is disabled since those words will just be
thrown away and the core will stall while they are being fetched.
These two changes make the performance using the disabled icache the
same as using non-icache prefetch buffer.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Amusingly, there was also actually a bug in the combo sequence logic:
it took seq_idx to be the number of sequences that we'd run so far,
but it is actually an index that chooses which sequence we're about to
run.
Follow OpenTitan's lead and move to Ubuntu 18.04 for the CI runner.
Ubuntu 16.04 comes with Python 3.5, which is EOL and causes more and
more issues.
Specificially, this update is triggered by rst2pdf not being installable
with pip's new dependency resolver (see also
https://github.com/rst2pdf/rst2pdf/issues/489#issuecomment-736652808).
dvsim.py runs make as a subprocess, which gets rather confused if
MAKEFLAGS appears in its environment. The proper fix is to clear them
from the environment in the dvsim command: we'll do that on the
OpenTitan side[1] and can revert this patch once that change is vendored
in.
[1] https://github.com/lowRISC/opentitan/pull/4325
This gets the rest of the support code needed for dvsim (which we
currently duplicate). The patch:
- adds the relevant directories to the vendoring file
- adds a patch to rewrite some OpenTitan-specific bits
- adds a "common_project_cfg.hjson"
- re-runs the vendoring tool
This patch won't yet change how DV code runs; we also need to redirect
a couple of paths and delete dv/uvm/data for that. This will happen in
the next patch.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This commit amends some paths in the vendoring hjson file (and updates
config files to use things at the new paths). Finally it re-runs the
vendoring tool:
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
92e9242424c72c59008e267dd3779e2af5ec8e83
which just ends up with a load of file renames.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
A few tweaks to fix broken links, make explanations more clear and
update the information to reflect the present (e.g. Spike master now
implements bit-manip, the seperate branch is gone).
- Make sure performance counters only count retired, non-trapping
instructions excluding ebrk/ecall
- Rewire some signalling through the writeback stage to allow
instruction retire to be signalled from one place
- Relates to #1132
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This makes changes to support Cadence Xcelium 20.09.001.
Cadence recommends that disabling forks should be done using a "disable fork;" statement, not the "disable fork_process_label;" construct.
The "disable fork_process_label" construct for forks is not defined in the IEEE Std 1800-2017 LRM. See section 9.6.2 of the LRM (2017).
For a more detailed explanation, please see the description from my colleague in Issue #1174: https://github.com/lowRISC/ibex/issues/1174.
In many cases, Xcelium will ignore a disable statement if it is not in the "disable fork;" form.
This causes problems in many tests, most notably in the riscv_reset_test.
Processes not being disabled when reset is asserted cause not just test failures, but the entire regression to crash.
Most changes here are simple substitutes of "disable fork;" where "disable label;" was.
Some changes in core_ibex_test_lib.sv require the layout of the fork to be adjusted.
Signed-off-by: CathalMCrevinn <cathal_minnock@crevinn.com>
This PR slightly modifies how we wait for the end of an Ibex sim.
Currently we wait on dut_vif.dut_cb.ecall, which will be delayed by a
cycle as it is in a clocking block.
However we should end the test immediately when an ecall is seen, so we
should rather wait on dut_vif.ecall instead to be more accurate and
prevent potential race conditions caused by irq/debug stimulus being
sent on the same cycle as an ecall instruction is executed by the core.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
- Reduce the size of the PMP address configuration registers to the
permissible minimum depending on granularity.
- Ensure consistency between PMP address CSR reads and the addresses
forwarded to the PMP module.
- Follow the specification more strictly, by returning bits
pmpaddr[G-2:0] as all ones when pmpcfg.A[1] is set (i.e. mode is
NAPOT or NA4, though the latter is invalid for G > 0) and bits
pmpaddr[G-1:0] as all zeros when pmpcfg.A[0] is clear (i.e. mode is
OFF or TOR).
- Fixes#1181
