Update code from upstream repository https://github.com/google/riscv-
dv to revision e3e1e308cfc3d718aeb94bb3463371979d9a31ae
* Disable full trace in the run script (google/riscv-dv#180) (taoliug)
* Fix spike logging issue (google/riscv-dv#179) (taoliug)
* Add functional coverage for HINT instructions (google/riscv-dv#177)
(taoliug)
* Add functional coverage for various hazard conditions (google/riscv-
dv#176) (taoliug)
Update code from upstream repository https://github.com/google/riscv-
dv to revision 44505927a70a6234b996d15f2e51bd1e2632b68e
* Dump performance counters to testbench at EOT (Udi)
* Fix a constraint issue (google/riscv-dv#174) (taoliug)
* Allow split a long test to small batches (google/riscv-dv#173)
(taoliug)
* Fix ius compile problem (google/riscv-dv#172) (taoliug)
* Add basic functional coverage for RV64IMC (google/riscv-dv#171)
(taoliug)
* Initial prototype of functional coverage (google/riscv-dv#169)
(taoliug)
The syntax of this statement is not correct without the `$fatal()` SV
construct. This causes errors in some tools even if the error condition
is not met.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 80d429475138b4b94d863030246a06980c89889d
* Fix mstatus randomization issue (google/riscv-dv#168) (taoliug)
* Lower the percentage of JAL instruction (google/riscv-dv#167)
(taoliug)
* Add an option to run a directed assembly test with ISS
(google/riscv-dv#166) (taoliug)
* Add memory fault handlers (Udi)
Give higher priority to data accesses from the CPU to improve
performance. This is the recommended setup for Ibex.
The test utility host needs still higher priority, otherwise the CPU
takes all bus capacity (the downside of strict priority arbitration).
Previously, verilated_toplevel.h contained a macro, VERILATED_TOPLEVEL()
to produce a class TOPLEVEL (whatever the toplevel happens to be). This
required all compilation units referring to that TOPLEVEL class to call
the macro.
After this change, the class is always generated in
verilated_toplevel.h. For that to work, a new define TOPLEVEL_NAME must
be globally set (e.g. passed to the compiler with -DTOPLEVEL_NAME=xxx).
- Fixes#288
- Add missing grant qualification to stop incorrect address updates
- Make RTL robust to spurious rvalid signalling
- Make sure a request is held until granted
- Remove incorrect assertion
Without this commit, the `nmi_mode` register is continuously cleared and
set again, and the core can never handle the NMI.
This resolveslowRISC/ibex#300 reported by @udinator.
This commit fixes the generation of the exception cause ID for fast
interrupts. Without this commit, the core tries to handle fast
interrupts using the handlers of other interrupts like external,
software, and timer interrupts.
This commit resolveslowRISC/ibex#290 reported by @udinator.
- See issue #265 (partially fixes)
- Remove path from instr_rvalid_i to instr_req_o
- Prefetch buffer unit can now issue up to two outstanding requests
- Structure moved from state machine to request queue
- Change fetch fifo to use an unaligned flag rather than updating
the address each time
- Relates to issue #265
- External signals data_rvalid_i and data_err_i were factored
into the external data_req_o signal
- To improve timing, these signals are decoupled
- The second part of an unaligned transaction will now be issued
even if the first received an error response
- The state machine will service the abandoned requests
- pmp_err_q fixed to only update at specific times
- The RISC-V Debug Spec v.0.13.2 (p.41) mandates that the core
debug CSRs dcsr, dpc, dscratch0 and dscratch1 must not be
accessible if not in debug mode. Fixes#275
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
Executing a DRET instruction outside of debug mode now causes an
illegal instruction exception as mandated by the Debug Spec v0.13.2
p.41.
This resolveslowRISC/ibex#270.
