Add a plusargs "+is_double_fault_detected_fatal" to the top-level cfg,
which is set to 1 by default.
Set the default for the "+enable_double_fault_detector" to 1.
Add a new scoreboard component to the core_ibex uvm environment, which contains
a double_fault detector task. This uses the top-level output
'double_fault_seen_o' to count the number of total and consecutive double_faults
seen with a test. A helper task allows the base_test to wait upon each of these
counters reaching the configured thresholds, and then to end the test early with
a passing result.
The default thresholds are 100 for consecutive faults, and 1000 for total faults.
The double_fault detector is disabled by default.
A plusarg '+enable_double_fault_detector=1' enables the checker.
This commit enables it for only the 'pmp_full_random_test', as that is a useful
test candidate to begin with.
Previously the time over which fetch enable was disabled was randomized
at the start of the sequence and kept constant throught. Now it is
randomized for every `send_req`.
Stop generating FetchEnableOn as a possible fetch_enable value to set
and use the SecureIbex parameter to decide if full randomisation off all
of the non FetchEnableOn MUBI values if needed or we just always switch
between FetchEnableOn/FetchEnableOff
Tweaks the default min/max delay values for how long fetch remains
disabled.
Previously `fetch_enable_i` only controlled the request going into the
instruction fetch stage. Due to buffering in the prefetch queue and
icache when this request is dropped it's possible for multiple
instructions to still be available for the ID/EX stage to consume. So
when `fetch_enable_i` was set to off you would get a 'soft stop'. Some
finite number of instructions may still execute and Ibex would come to
an eventual halt.
Now `fetch_enable_i` also gates the instruction moving between the fetch
stage and the ID/EX stage. This gives a 'hard stop' where once fetch is
disabled Ibex comes to an immediate halt.
This commit changes when we cath the debug causes. Since debug_cause_o
only gets latched when `csr_save_cause_o` is high, it would work if
we change the cause with a mux that is connected to the input signals.
Resolves#1772
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Previously Ibex signalled a major alert on an integrity error (where
incoming read data doesn't match its integrity bits) for both read and
write responses. This was removed as the data part of a response to a
write is ignored.
This brings it back in a more measured way. This provides a little extra
fault injection hardening as an attacker glitching the memory bus will
generate an alert on both read and write responses.
This test doesn't actually check the performance counters, it just runs
a random instruction test and dumps the performance counters at the end
for some final checking. That checking does not exist. The test is
currently broken as well so just remove it as it adds nothing to the
regression.
Update code from upstream repository https://github.com/google/riscv-
dv to revision c6acc1897429f5245cc89b2ecee2e3eefdefd18d
* Add plusarg to enable ECALL insn in main randomized body (Harry
Callahan)
Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
This commit adds another field in SpikeCosim class so that Spike
can hardcode the correct event registers.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Previously it was sourced from the OpenSUSE build service. This has
produced some reliability issues. Downloading pre-built binaries from a
GCP bucket should improve things.
This addresses a current testbench issue where asserting debug_req_i close to
when single_stepping over an instruction causes an incorrect 'cause' to be
recorded within DCSR.
This builds upon the cosimulation environment to allow us to rip-out all the
existing checking from the test, and instead focus on generating good stimulus
to hit all our coverage points.
Make use of the riscv-dv changes to insert ecall into the main test body, now
that we have a different mechanism for ending the test.
Allow illegal instructions, csr instructions, ebreak, etc. which the previous
brittle checking paradigms could not handle.
This commit adds a new field to the trr (test-run-result) structured data
that records the failure_mode of a testcase. If the test failed due to a
timeout, print a small addendum {T} to each log-line in the summary.
eg.
23.33% PASS 7 PASSED, 23 FAILED
riscv_debug_basic_test.21259: PASS
riscv_debug_basic_test.21260: FAILED {T}
riscv_debug_basic_test.21261: PASS
riscv_debug_basic_test.21262: FAILED {T}
riscv_debug_basic_test.21263: FAILED {T}
riscv_debug_instr_test.21259: FAILED {T}
riscv_debug_instr_test.21260: FAILED {T}
riscv_debug_instr_test.21261: FAILED {T}
riscv_debug_instr_test.21262: PASS
riscv_debug_instr_test.21263: FAILED {T}
riscv_dret_test.21259: FAILED
riscv_dret_test.21260: FAILED
riscv_dret_test.21261: FAILED {T}
Observing the spec change:
RISC-V Debug Support Version 1.0.0-STABLE
1.2.1.4 New Features from 0.13 to 1.0
> 8. Move scontext, renaming original to mscontext, and create hcontext. #535
MSCONTEXT is a backwards-compatible alias to SCONTEXT
In Ibex, SCONTEXT is a read-only zero register. Hence MSCONTEXT has the same behaviour.
