30 commits

Author	SHA1	Message	Date
Olof Kindgren	c9a3c883f1	Refactor testbench ... Introduce an intermediate common simulation toplevel for verilator and other sims	2020-03-03 09:15:50 +01:00
Olof Kindgren	ed02951b4d	Add vcd_start parameter	2019-11-19 10:46:15 +01:00
Olof Kindgren	9c83e39635	Initialize state of verilator UART decoder	2019-11-04 13:01:31 +01:00
Olof Kindgren	57b4fca05f	Ignore initial garbage in verilator UART decoder	2019-10-29 21:53:13 +01:00
Olof Kindgren	e059b7cf09	Add timeout argument	2019-08-25 22:52:34 +02:00
Olof Kindgren	70bdce9d8e	Refactor gpio/uart output in tb	2019-06-24 13:18:34 +02:00
Olof Kindgren	cf7e516526	Refactor to separate serv and servant	2019-06-24 13:18:34 +02:00
Olof Kindgren	bba836ad8c	Fix width mismatches to make code verilator clean	2019-03-25 20:57:13 +01:00
Olof Kindgren	836a013462	Fix clock generation	2018-12-06 22:12:03 +01:00
Olof Kindgren	fc82862e96	Add icepll generator and run tinyfpga BX at 32MHz	2018-12-03 12:26:17 +01:00
Olof Kindgren	ec8252ea0a	Add memsize parameter	2018-11-26 17:54:10 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	12039dec0e	Add support for setting memory contents during synthesis	2018-11-26 09:49:08 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	079d973969	Cleanup	2018-11-21 13:22:55 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	6e034361d4	Add UART decoder	2018-11-19 09:42:42 +01:00
Olof Kindgren	ff63519607	Temporary hack to blink LED on tinyfpga BX	2018-11-18 21:42:42 +01:00
Olof Kindgren	2062d084bf	Disable GPIO output in verilator	2018-11-18 21:40:51 +01:00
Olof Kindgren	7666ac4092	synthesized netlist works	2018-11-18 13:05:38 +01:00
Olof Kindgren	d4102f927f	Synthesis fixes	2018-11-17 22:14:44 +01:00
Olof Kindgren	0362192769	Use internal reset	2018-11-17 22:06:10 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	a92c933af1	csr, verilator, traps	2018-11-14 12:16:20 +01:00
Olof Kindgren	3c98d35766	Change to wb interface	2018-11-09 21:26:13 +01:00
Olof Kindgren	8409aa4c4b	lh, lw, lbu, lhu, sb, sh, slti	2018-11-01 22:51:51 +01:00
Olof Kindgren	96b1906676	bne, srai	2018-10-30 22:41:05 +01:00
Olof Kindgren	c2030a95fd	jal, addi, lui, lb	2018-10-26 22:52:39 +02:00
Olof Kindgren	e10c41be8d	Initial commit	2018-10-23 23:45:41 +02:00