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Author	SHA1	Message	Date
Olof Kindgren	0e63e979e4	wip	2023-03-16 11:52:16 +01:00
Olof Kindgren	109acd0a53	Prepare for release	2022-12-25 22:04:52 +01:00
Olof Kindgren	5fa5c5c3c3	Sort all sections in servant.core	2022-12-25 21:49:19 +01:00
Olof Kindgren	9be55f5cad	Set align parameter to the value of compressed by default	2022-12-25 21:34:48 +01:00
Abdulwadoodd	04991380df	GitHub actions for updated Compliance testing	2022-12-25 21:23:51 +01:00
Abdulwadoodd	174330d06e	Updated readme and added instructions to run compliance tests	2022-12-25 21:23:51 +01:00
Abdulwadoodd	121099bf54	Add SAIL-RISCV binaries with reamde instructions	2022-12-25 21:23:51 +01:00
Abdulwadoodd	c1a275db49	Added arch-tests as a submodule	2022-12-25 21:23:51 +01:00
Abdulwadoodd	41ae06f6cf	Update Compliance testing framework	2022-12-25 21:23:51 +01:00
Abdulwadoodd	1bdd42acb5	Deleted old compliance framework	2022-12-25 21:23:51 +01:00
Olof Kindgren	76a75995b9	Remove RVFI interface from synth wrapper	2022-12-25 20:05:52 +01:00
Olof Kindgren	9c1685e07e	Add Servant documentation	2022-12-18 18:09:54 +01:00
Olof Kindgren	7c004e8f7b	Add reset input for Arty A7 target	2022-10-16 20:04:56 +02:00
gojimmypi	6ad60f69a2	Add ICE-V Wireless support	2022-10-13 10:23:13 +02:00
Olof Kindgren	7abd9bbbe1	serving: Tie off extension interface	2022-10-13 09:58:21 +02:00
Eric Brombaugh	5cc7b0cbe1	Guarantee at least 2 cycles of o_rst after PLL locked.	2022-08-10 09:02:51 +00:00
Olof Kindgren	cb4276e8b2	Prepare for release	2022-07-26 01:19:28 +02:00
Olof Kindgren	efe8ba832a	Set up Github CI testing matrix for compliance tests	2022-07-26 00:28:53 +02:00
Abd	0cce381316	Add Nexys 2 target info	2022-07-26 00:28:53 +02:00
Olof Kindgren	73508bc5de	Expose with_csr in servant	2022-07-26 00:28:53 +02:00
Abdulwadoodd	be06cd21c2	Right version of riscv-arch-test	2022-07-26 00:28:53 +02:00
Abd	1beb9d33ec	privilege tests fixed for rv32i	2022-07-26 00:28:53 +02:00
Inoki	302224834b	Add description for AX309 board target	2022-06-13 12:21:05 +00:00
Inoki	e996b5498a	Add Alinx AX309 board as a target ... Running at 32MHz with 115200 baud rate UART (using the on-board RS232)	2022-06-13 12:21:05 +00:00
Olof Kindgren	2611c89cbe	Update support for compliance tests version 2.7.4	2022-06-13 12:02:27 +00:00
Abd	a8f7de9e8c	compressed parameter added for Nexys-2 FPGA target	2022-06-13 10:38:36 +00:00
Abd	82b410f500	Update reamde, comments and paramters	2022-06-13 10:38:11 +00:00
Abd	2655861447	Compressed Extension for SERV	2022-06-01 13:38:24 +02:00
Wadood	4ddd154b24	Nexys 2 Board support ... Added nexys 2 target support for servant	2022-05-17 09:11:56 +02:00
Usman	2df592340f	Compliance update ... Updated serv to support latest version of riscv-arch-test (v2.6.1)	2022-04-13 07:48:58 +02:00
Olof Kindgren	7d08abb92d	Improve makehex.py	2022-03-09 21:00:06 +01:00
Olof Kindgren	2bb988b553	Add reset for mie_mtie	2022-02-09 18:15:08 +01:00
Olof Kindgren	b74344bb48	Store GDS file as artifact after OpenLANE build	2022-01-21 00:11:32 +01:00
somhi	09e49f784a	added board_device_index : 2 to chameleon96 for programming	2022-01-13 23:11:12 +01:00
somhi	7624365325	chameleon96 board support added (#74) ... * chameleon96 board added	2022-01-11 22:54:45 +01:00
Olof Kindgren	e59fe5346a	Refactor docs and add interface documentation	2022-01-03 18:12:48 +01:00
Olof Kindgren	a121b19ec4	Document shift operations	2022-01-02 23:54:13 +01:00
Olof Kindgren	aa8550b937	Remove doc for removed modules	2022-01-02 22:10:33 +01:00
Olof Kindgren	d910becd7f	Move dbus_dat/rs2/shamt storage to bufreg2	2022-01-02 22:10:33 +01:00
Olof Kindgren	f04a510393	Remove unused parameter from serv_mem_if	2022-01-01 22:50:28 +01:00
Olof Kindgren	0719381997	Add ViDBo support	2022-01-01 17:15:14 +01:00
Olof Kindgren	0ab7176d3b	Fix testbench indentation	2022-01-01 17:15:14 +01:00
Olof Kindgren	7765567cf1	Add missing gate on mem_rd with CSR disabled	2021-12-29 00:17:00 +01:00
Olof Kindgren	28953fec4c	Simplify shift_op signal	2021-10-08 22:42:02 +02:00
Olof Kindgren	9c4bdd4bfe	Simplify branch_op/slt_op signals	2021-10-08 22:25:24 +02:00
Olof Kindgren	9d3ebf3e96	Replace mem_op with dedicated control signals	2021-10-05 12:52:29 +02:00
Olof Kindgren	e5c6e78820	Simplify MDU logic in serv_mem_if	2021-10-04 23:49:23 +02:00
Olof Kindgren	99f82af6eb	Simplify optional MDU logic	2021-10-03 23:28:45 +02:00
Zeeshan Rafique	8843005407	updated vars declaration for modelsim (#63)	2021-10-03 23:15:54 +02:00
Olof Kindgren	48e250ea5e	Clean up serv_state interface	2021-10-03 22:48:51 +02:00