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216 commits

Author SHA1 Message Date
Olof Kindgren
9be55f5cad Set align parameter to the value of compressed by default 2022-12-25 21:34:48 +01:00
Olof Kindgren
76a75995b9 Remove RVFI interface from synth wrapper 2022-12-25 20:05:52 +01:00
Olof Kindgren
73508bc5de Expose with_csr in servant 2022-07-26 00:28:53 +02:00
Abd
1beb9d33ec privilege tests fixed for rv32i 2022-07-26 00:28:53 +02:00
Abd
82b410f500 Update reamde, comments and paramters 2022-06-13 10:38:11 +00:00
Abd
2655861447 Compressed Extension for SERV 2022-06-01 13:38:24 +02:00
Olof Kindgren
2bb988b553 Add reset for mie_mtie 2022-02-09 18:15:08 +01:00
Olof Kindgren
d910becd7f Move dbus_dat/rs2/shamt storage to bufreg2 2022-01-02 22:10:33 +01:00
Olof Kindgren
f04a510393 Remove unused parameter from serv_mem_if 2022-01-01 22:50:28 +01:00
Olof Kindgren
7765567cf1 Add missing gate on mem_rd with CSR disabled 2021-12-29 00:17:00 +01:00
Olof Kindgren
28953fec4c Simplify shift_op signal 2021-10-08 22:42:02 +02:00
Olof Kindgren
9c4bdd4bfe Simplify branch_op/slt_op signals 2021-10-08 22:25:24 +02:00
Olof Kindgren
9d3ebf3e96 Replace mem_op with dedicated control signals 2021-10-05 12:52:29 +02:00
Olof Kindgren
e5c6e78820 Simplify MDU logic in serv_mem_if 2021-10-04 23:49:23 +02:00
Olof Kindgren
99f82af6eb Simplify optional MDU logic 2021-10-03 23:28:45 +02:00
Zeeshan Rafique
8843005407
updated vars declaration for modelsim (#63) 2021-10-03 23:15:54 +02:00
Olof Kindgren
48e250ea5e Clean up serv_state interface 2021-10-03 22:48:51 +02:00
Klas Nordmark
52d0bf0938 Added openlane target and params.tcl with suitable openlane parameters for SERV 2021-08-30 22:13:42 +02:00
Olof Kindgren
2989051f44 Avoid enabling bufreg before instruction is decoded 2021-08-27 13:10:06 +02:00
Olof Kindgren
3971ca942e Fix up RVFI 2021-08-27 13:10:06 +02:00
Olof Kindgren
64f5ca0b7f Add missing reset on cnt_done 2021-08-27 13:10:06 +02:00
Olof Kindgren
781c07b7dc Properly reset stage_two_req signal 2021-08-27 13:10:06 +02:00
Olof Kindgren
b10a871499 Fix signedness bug on immediates 
The sign bit on immediates relied on the value of csr_imm_en from
the previous instruction. This fixes by gating with csr_imm_en
after it has been latched instead of before
 2021-08-27 13:10:06 +02:00
Olof Kindgren
d2a4243033 Add reset for new_irq register 2021-08-27 13:10:06 +02:00
Olof Kindgren
621baeff31 Always return 0 from reads to reg x0 in serv_rf_ram 2021-08-27 13:10:06 +02:00
Zeeshan Rafique
6e802cb9bc M-extension support for SERV 
* modified serv(ant) for MDU
* added dependency for mdu
* M-extension for SERV
* Updated README for running RV32IM compliance tests
* waive some lint warnings related to mdu
* added mdu param for arty_a7_35t
 2021-08-20 23:45:19 +02:00
Olof Kindgren
c2cdd44f73 Expose and document PRE_REGISTER 2021-06-05 22:56:37 +02:00
Sylvain Munaut
259d5a10ed decode: Add option to pre or post register during decoding 
Either the input from instruction bus is registered and the
outputs are generated combinatorially (PRE_REGISTER mode), or
the input from the instruction bus is decoded combinatorially
and the result of decoding is registered (POST_REGISTER mode).

First is smaller because it allows synthesis to optimize decoding
logic with its users, but is slow. The second one is faster but
slightly bigger.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-05-28 21:26:54 +02:00
Olof Kindgren
f373d7bcb6 Reuse immediate regs for RF addresses 2021-05-16 00:09:18 +02:00
Olof Kindgren
14262bfc30 Rewrite logic expression of alu bool operations 2021-05-15 23:07:55 +02:00
Olof Kindgren
a5c1c8ddc4 Kill off serv_params.vh 2021-04-26 17:04:18 +02:00
Olof Kindgren
1c11365ae8 Simulator-friendly cleanup of misalign_trap_sync 2021-04-22 15:44:18 +02:00
Olof Kindgren
82c808aa1e Implement byte_valid in a more efficient way 2021-04-18 22:48:55 +02:00
Olof Kindgren
62d5d5f8fb Remove unused wire cnt4 2021-04-18 22:01:32 +02:00
Olof Kindgren
0c601f0872 Fix RF we gating for RF width > 2 2021-04-18 00:13:47 +02:00
Olof Kindgren
079a5c4250 Remove unused wgo register 2021-04-08 15:36:11 +02:00
Olof Kindgren
548b7fbb41 remove redundant ALU control signal 2021-03-14 23:22:50 +01:00
Olof Kindgren
727bb40a87 Simplify control logic for bool ops 2021-03-14 00:12:29 +01:00
Olof Kindgren
7624466ddd Optimize serv_rf_ram_if 2021-02-15 08:50:24 +01:00
Olof Kindgren
9a0b0e877c Move shifter to mem_if 
This allows reusing the data bus registers for shift amount
 2021-02-06 23:24:23 +01:00
Olof Kindgren
f70b79fd8f Combine lt and eq regs to cmp_r in serv_alu 2021-02-01 22:37:45 +01:00
Olof Kindgren
6fbdea58d6 Optimize trap handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
8d5dd77a26 Optimize csr address handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
e4b773c17b Syntax fixes 2021-01-18 22:47:28 +01:00
Olof Kindgren
5e4181d204 Optimize shift operations 2021-01-18 22:46:51 +01:00
Olof Kindgren
d5febe8f63 Simplify and document trap handling 2021-01-18 22:38:07 +01:00
Olof Kindgren
17103dd1f5 Merge LSB registers into bufreg 2021-01-11 21:40:45 +01:00
Olof Kindgren
fe6c9b0f83 Optimize bufreg lsb signal and clean up bufreg interface 2021-01-06 22:19:40 +01:00
Olof Kindgren
0bc19ef13c Clean up serv_alu interface 2021-01-06 22:02:13 +01:00
Olof Kindgren
ace7b8ef44 Explain and optimize state counter 2021-01-03 00:01:09 +01:00