216 commits

Author	SHA1	Message	Date
Olof Kindgren	16c93a58ee	Move mepc and mtval into RF memory	2019-07-08 07:49:58 +02:00
Olof Kindgren	93f7b582bb	Remove unused localparam	2019-07-08 07:47:45 +02:00
AlAlves	2fb56ac62d	Update serv_top.v	2019-07-08 07:47:12 +02:00
Olof Kindgren	e107627e71	Reduce warnings	2019-06-24 15:22:08 +02:00
Olof Kindgren	fe9d2677ba	Add SERV_CLEAR_RAM parameter	2019-06-24 13:18:34 +02:00
Olof Kindgren	bad78b0bd7	Declare wires before use	2019-06-24 13:18:34 +02:00
Olof Kindgren	cf7e516526	Refactor to separate serv and servant	2019-06-24 13:18:34 +02:00
Olof Kindgren	42ac1e5e4d	Store CSR in RF RAM ... Since FPGA uses fixed-size RAM, it's better in most cases to store the CSR in unused memory positions in that RAM. Since the decoding is made more complex, the old register file implementation is kept around since that is more efficient when we don't want CSR and potentially when the FPGA support hardware shift registers.	2019-06-07 19:39:18 +02:00
Olof Kindgren	b0a062ae21	Speed up instruction fetching	2019-04-12 08:15:08 +02:00
Olof Kindgren	bba836ad8c	Fix width mismatches to make code verilator clean	2019-03-25 20:57:13 +01:00
Olof Kindgren	3438e0f172	Optimize mcause CSR	2019-03-21 09:24:11 +01:00
Olof Kindgren	6e91409990	Optimize alu eq check	2019-03-20 08:35:43 +01:00
Olof Kindgren	a550137453	Use bufreg for shifter	2019-03-20 08:35:43 +01:00
Olof Kindgren	fe33d6abdc	Move dbus address handling to global bufreg	2019-01-15 08:00:32 +01:00
Olof Kindgren	9a97c535bd	Use ring buffer for counter LSBs	2019-01-15 08:00:32 +01:00
Olof Kindgren	215da65e82	Optimize serv_mem_if	2019-01-15 08:00:32 +01:00
Olof Kindgren	6f4c85f16d	Optimize alu_sub control flag	2019-01-15 08:00:32 +01:00
Olof Kindgren	45f6d408f8	Remove dead code	2019-01-15 08:00:32 +01:00
Olof Kindgren	3a68cc0e77	Improve critical path in ctrl	2019-01-15 08:00:32 +01:00
Olof Kindgren	813f9f4951	Rewrite CSR selection	2019-01-10 18:15:20 +01:00
Olof Kindgren	f5a1590422	Remove duplicated adder+inverter	2019-01-10 18:15:20 +01:00
Olof Kindgren	ba79ffdf0b	Prevent writes to x0	2019-01-10 18:15:20 +01:00
Olof Kindgren	8ae05ea4cf	Rewrite immediate decoder	2018-12-25 13:13:04 +01:00
Olof Kindgren	78821c16b3	Optimize op_b selector	2018-12-25 13:13:04 +01:00
Olof Kindgren	e3e616903e	Optimize bool operations	2018-12-25 13:13:04 +01:00
Olof Kindgren	4a224fc985	Fix failing compliance tests	2018-12-13 12:03:42 +01:00
Olof Kindgren	3f5c25d8f2	Silence LSE warnings	2018-12-12 21:20:44 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	af1d4da8bf	Fix rvfi logic	2018-12-11 22:02:03 +01:00
Olof Kindgren	f627aee1a1	Syntax fixes to please Vivado	2018-12-07 23:20:47 +01:00
Olof Kindgren	468e99ac7c	Syntax fixes to please Quartus	2018-12-07 22:55:55 +01:00
Olof Kindgren	6cd3d2d3ef	Fix rvfi_insn	2018-12-06 23:47:52 +01:00
Olof Kindgren	836a013462	Fix clock generation	2018-12-06 22:12:03 +01:00
Olof Kindgren	fc82862e96	Add icepll generator and run tinyfpga BX at 32MHz	2018-12-03 12:26:17 +01:00
Olof Kindgren	cd983190b3	Interrupts working. Adding philosophers example	2018-11-26 23:03:40 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	12039dec0e	Add support for setting memory contents during synthesis	2018-11-26 09:49:08 +01:00
Olof Kindgren	e1f5bcc4f3	Rewrite register file	2018-11-26 00:09:52 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	458d12c81d	Remove dead code	2018-11-22 13:10:28 +01:00
Olof Kindgren	fa8def6e7a	Rewrite immediate decoding	2018-11-22 13:02:51 +01:00
Olof Kindgren	f15cab5458	Fix linter complaints	2018-11-21 13:25:37 +01:00
Olof Kindgren	079d973969	Cleanup	2018-11-21 13:22:55 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	6e034361d4	Add UART decoder	2018-11-19 09:42:42 +01:00
Olof Kindgren	ff63519607	Temporary hack to blink LED on tinyfpga BX	2018-11-18 21:42:42 +01:00
Olof Kindgren	7666ac4092	synthesized netlist works	2018-11-18 13:05:38 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00