41 commits

Author	SHA1	Message	Date
Olof Kindgren	d910becd7f	Move dbus_dat/rs2/shamt storage to bufreg2	2022-01-02 22:10:33 +01:00
Olof Kindgren	f04a510393	Remove unused parameter from serv_mem_if	2022-01-01 22:50:28 +01:00
Olof Kindgren	9d3ebf3e96	Replace mem_op with dedicated control signals	2021-10-05 12:52:29 +02:00
Olof Kindgren	e5c6e78820	Simplify MDU logic in serv_mem_if	2021-10-04 23:49:23 +02:00
Zeeshan Rafique	6e802cb9bc	M-extension support for SERV ... * modified serv(ant) for MDU * added dependency for mdu * M-extension for SERV * Updated README for running RV32IM compliance tests * waive some lint warnings related to mdu * added mdu param for arty_a7_35t	2021-08-20 23:45:19 +02:00
Olof Kindgren	82c808aa1e	Implement byte_valid in a more efficient way	2021-04-18 22:48:55 +02:00
Olof Kindgren	9a0b0e877c	Move shifter to mem_if ... This allows reusing the data bus registers for shift amount	2021-02-06 23:24:23 +01:00
Olof Kindgren	d5febe8f63	Simplify and document trap handling	2021-01-18 22:38:07 +01:00
Olof Kindgren	25fa6fa83b	Clean up and document serv_mem_if	2021-01-02 00:02:23 +01:00
Olof Kindgren	fda7dd288a	Optimize enable signal for mem_if buffers	2020-04-15 22:48:28 +02:00
Olof Kindgren	6b0e4fb3ea	Disable misalignment traps when CSR is disabled	2020-03-27 08:55:34 +01:00
Olof Kindgren	36746d3890	Remove unused signals	2020-02-17 23:01:49 +01:00
Olof Kindgren	2b5c71fe9b	Gate mem_rd in mem_if	2019-09-26 23:31:23 +02:00
Olof Kindgren	0f767ad2d3	Gate mem_misalign in mem_if	2019-09-26 23:23:42 +02:00
Olof Kindgren	d4c782bce6	Set o_dbus_we directly from decode	2019-09-16 00:13:21 +02:00
Olof Kindgren	b9e410a0a0	Remove bytepos from serv_mem_if	2019-09-16 00:07:58 +02:00
Olof Kindgren	5a44634ee5	Avoid exposing funct3 from decode	2019-09-15 23:50:02 +02:00
Olof Kindgren	8dc137fb07	Kill of mem_init and mem_en	2019-09-13 23:30:46 +02:00
Olof Kindgren	e20e0eef8f	Optimize dbus_cyc	2019-09-13 23:30:46 +02:00
Olof Kindgren	892388627c	Speed up memory accesses	2019-08-14 22:15:45 +02:00
Olof Kindgren	bad78b0bd7	Declare wires before use	2019-06-24 13:18:34 +02:00
Olof Kindgren	a550137453	Use bufreg for shifter	2019-03-20 08:35:43 +01:00
Olof Kindgren	fe33d6abdc	Move dbus address handling to global bufreg	2019-01-15 08:00:32 +01:00
Olof Kindgren	215da65e82	Optimize serv_mem_if	2019-01-15 08:00:32 +01:00
Olof Kindgren	4a224fc985	Fix failing compliance tests	2018-12-13 12:03:42 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	0036756157	Pass compliance tests	2018-11-15 14:16:01 +01:00
Olof Kindgren	f12f8ecf61	Remove MEM_WAIT state	2018-11-15 09:59:25 +01:00
Olof Kindgren	aa0e3aa77e	Handle misaligned jal	2018-11-15 08:49:29 +01:00
Olof Kindgren	a92c933af1	csr, verilator, traps	2018-11-14 12:16:20 +01:00
Olof Kindgren	3c98d35766	Change to wb interface	2018-11-09 21:26:13 +01:00
Olof Kindgren	8409aa4c4b	lh, lw, lbu, lhu, sb, sh, slti	2018-11-01 22:51:51 +01:00
Olof Kindgren	d4bbe17e78	jalr, blt	2018-10-31 14:51:28 +01:00
Olof Kindgren	96b1906676	bne, srai	2018-10-30 22:41:05 +01:00
Olof Kindgren	66000a77f5	beq, sw	2018-10-28 23:54:04 +01:00
Olof Kindgren	c2030a95fd	jal, addi, lui, lb	2018-10-26 22:52:39 +02:00