94 commits

Author	SHA1	Message	Date
Olof Kindgren	31852f175d	Simplify alu_cmp_eq control logic	2019-07-23 12:10:38 +02:00
Olof Kindgren	af3b82f9ac	Optimize take_branch condition	2019-07-23 12:10:38 +02:00
Olof Kindgren	16c93a58ee	Move mepc and mtval into RF memory	2019-07-08 07:49:58 +02:00
Olof Kindgren	e107627e71	Reduce warnings	2019-06-24 15:22:08 +02:00
Olof Kindgren	bad78b0bd7	Declare wires before use	2019-06-24 13:18:34 +02:00
Olof Kindgren	a550137453	Use bufreg for shifter	2019-03-20 08:35:43 +01:00
Olof Kindgren	9a97c535bd	Use ring buffer for counter LSBs	2019-01-15 08:00:32 +01:00
Olof Kindgren	6f4c85f16d	Optimize alu_sub control flag	2019-01-15 08:00:32 +01:00
Olof Kindgren	45f6d408f8	Remove dead code	2019-01-15 08:00:32 +01:00
Olof Kindgren	3a68cc0e77	Improve critical path in ctrl	2019-01-15 08:00:32 +01:00
Olof Kindgren	813f9f4951	Rewrite CSR selection	2019-01-10 18:15:20 +01:00
Olof Kindgren	8ae05ea4cf	Rewrite immediate decoder	2018-12-25 13:13:04 +01:00
Olof Kindgren	78821c16b3	Optimize op_b selector	2018-12-25 13:13:04 +01:00
Olof Kindgren	e3e616903e	Optimize bool operations	2018-12-25 13:13:04 +01:00
Olof Kindgren	4a224fc985	Fix failing compliance tests	2018-12-13 12:03:42 +01:00
Olof Kindgren	3f5c25d8f2	Silence LSE warnings	2018-12-12 21:20:44 +01:00
Olof Kindgren	09bb05071e	Fix bugs and missing resets to pass formal	2018-12-11 22:05:32 +01:00
Olof Kindgren	cd983190b3	Interrupts working. Adding philosophers example	2018-11-26 23:03:40 +01:00
Olof Kindgren	11a2195146	First attempt att interrupt support	2018-11-26 16:01:07 +01:00
Olof Kindgren	12039dec0e	Add support for setting memory contents during synthesis	2018-11-26 09:49:08 +01:00
Olof Kindgren	e1f5bcc4f3	Rewrite register file	2018-11-26 00:09:52 +01:00
Olof Kindgren	a974320f46	Further optimizations	2018-11-23 21:26:49 +01:00
Olof Kindgren	b8f5133267	Random optimizations	2018-11-23 13:59:07 +01:00
Olof Kindgren	1bbf8e3ce9	Synthesis fixes	2018-11-22 20:58:45 +01:00
Olof Kindgren	fa8def6e7a	Rewrite immediate decoding	2018-11-22 13:02:51 +01:00
Olof Kindgren	9df2a0060b	Use custom interconnect. Runs on hw	2018-11-21 13:15:33 +01:00
Olof Kindgren	7666ac4092	synthesized netlist works	2018-11-18 13:05:38 +01:00
Olof Kindgren	f66f82a57a	Add explicit wire defs to ports	2018-11-17 21:30:03 +01:00
Olof Kindgren	0036756157	Pass compliance tests	2018-11-15 14:16:01 +01:00
Olof Kindgren	34fc93ba09	Fix misaligned jumps	2018-11-15 12:50:40 +01:00
Olof Kindgren	f12f8ecf61	Remove MEM_WAIT state	2018-11-15 09:59:25 +01:00
Olof Kindgren	91cff7fdfc	Merge COMPARE and SH_INIT states	2018-11-15 09:02:18 +01:00
Olof Kindgren	aa0e3aa77e	Handle misaligned jal	2018-11-15 08:49:29 +01:00
Olof Kindgren	a92c933af1	csr, verilator, traps	2018-11-14 12:16:20 +01:00
Olof Kindgren	3c98d35766	Change to wb interface	2018-11-09 21:26:13 +01:00
Olof Kindgren	cbbdaed112	slli, srli, add, sll, sltiu, slt, xor, srl, sra, or, and	2018-11-02 13:48:08 +01:00
Olof Kindgren	8409aa4c4b	lh, lw, lbu, lhu, sb, sh, slti	2018-11-01 22:51:51 +01:00
Olof Kindgren	c90920d9b2	bge, bltu, bgeu	2018-11-01 09:35:49 +01:00
Olof Kindgren	d4bbe17e78	jalr, blt	2018-10-31 14:51:28 +01:00
Olof Kindgren	d4b2697761	auipc, sub	2018-10-30 23:33:28 +01:00
Olof Kindgren	96b1906676	bne, srai	2018-10-30 22:41:05 +01:00
Olof Kindgren	66000a77f5	beq, sw	2018-10-28 23:54:04 +01:00
Olof Kindgren	c2030a95fd	jal, addi, lui, lb	2018-10-26 22:52:39 +02:00
Olof Kindgren	e10c41be8d	Initial commit	2018-10-23 23:45:41 +02:00