github-mirrors/serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2025-04-23 05:17:06 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
408 commits 8 branches 8 tags 17 MiB
Commit graph

94 commits

Author SHA1 Message Date
Olof Kindgren
bc74a9a1d7 Used named generate statements 
Unnamed generate statements are not recommended and some tools throw
warnings or errors for these.
 2023-11-16 21:38:10 +01:00
Abd
2655861447 Compressed Extension for SERV 2022-06-01 13:38:24 +02:00
Olof Kindgren
28953fec4c Simplify shift_op signal 2021-10-08 22:42:02 +02:00
Olof Kindgren
9c4bdd4bfe Simplify branch_op/slt_op signals 2021-10-08 22:25:24 +02:00
Olof Kindgren
9d3ebf3e96 Replace mem_op with dedicated control signals 2021-10-05 12:52:29 +02:00
Olof Kindgren
e5c6e78820 Simplify MDU logic in serv_mem_if 2021-10-04 23:49:23 +02:00
Olof Kindgren
99f82af6eb Simplify optional MDU logic 2021-10-03 23:28:45 +02:00
Zeeshan Rafique
8843005407
updated vars declaration for modelsim (#63) 2021-10-03 23:15:54 +02:00
Zeeshan Rafique
6e802cb9bc M-extension support for SERV 
* modified serv(ant) for MDU
* added dependency for mdu
* M-extension for SERV
* Updated README for running RV32IM compliance tests
* waive some lint warnings related to mdu
* added mdu param for arty_a7_35t
 2021-08-20 23:45:19 +02:00
Olof Kindgren
c2cdd44f73 Expose and document PRE_REGISTER 2021-06-05 22:56:37 +02:00
Sylvain Munaut
259d5a10ed decode: Add option to pre or post register during decoding 
Either the input from instruction bus is registered and the
outputs are generated combinatorially (PRE_REGISTER mode), or
the input from the instruction bus is decoded combinatorially
and the result of decoding is registered (POST_REGISTER mode).

First is smaller because it allows synthesis to optimize decoding
logic with its users, but is slow. The second one is faster but
slightly bigger.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-05-28 21:26:54 +02:00
Olof Kindgren
f373d7bcb6 Reuse immediate regs for RF addresses 2021-05-16 00:09:18 +02:00
Olof Kindgren
a5c1c8ddc4 Kill off serv_params.vh 2021-04-26 17:04:18 +02:00
Olof Kindgren
548b7fbb41 remove redundant ALU control signal 2021-03-14 23:22:50 +01:00
Olof Kindgren
727bb40a87 Simplify control logic for bool ops 2021-03-14 00:12:29 +01:00
Olof Kindgren
9a0b0e877c Move shifter to mem_if 
This allows reusing the data bus registers for shift amount
 2021-02-06 23:24:23 +01:00
Olof Kindgren
8d5dd77a26 Optimize csr address handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
5e4181d204 Optimize shift operations 2021-01-18 22:46:51 +01:00
Olof Kindgren
a960fd768b Remove redundant bufreg_loop control signal 2020-12-22 22:13:57 +01:00
Olof Kindgren
d6445b95a6 Clean up serv_ctrl 2020-12-06 22:39:04 +01:00
Olof Kindgren
3f81f07db3 Clarify immdec_ctrl[1] 2020-11-10 15:16:19 +01:00
Olof Kindgren
8faf0cf33b Simplify and explain csr_imm_en 2020-11-10 15:16:19 +01:00
Olof Kindgren
915cdf7933 Move RF address decoding to serv_immdec 2020-08-17 13:00:29 +02:00
Olof Kindgren
88a1a43438 Refactor and Use ALU subtractor for comparisons 2020-08-13 23:37:11 +02:00
Olof Kindgren
1c4e793885 Move CSR immediate decoder to immdec 2020-08-13 23:37:11 +02:00
Olof Kindgren
8775b321d9 Move jump decision logic to serv_state 2020-08-13 23:37:11 +02:00
Olof Kindgren
a614e427b8 Move immediate decoder to separate module 2020-08-13 23:37:11 +02:00
dh73
2a7596b51d Declare variables/nets before referenced 2020-03-25 23:31:55 +01:00
Olof Kindgren
7f16f17ca5 Optimize CSR immediate handling 2020-02-19 10:02:48 +01:00
Olof Kindgren
36746d3890 Remove unused signals 2020-02-17 23:01:49 +01:00
Olof Kindgren
5aa1fbe709 Stop depending on run state 2019-12-08 22:51:28 +01:00
Olof Kindgren
6067b0e684 Use one-hot encoding for ALU rd sel 2019-12-07 23:36:36 +01:00
Olof Kindgren
98bfcc3b62 Remove unused jalr signal 2019-10-30 09:07:58 +01:00
Olof Kindgren
75decc8251 Bring back old immediate decoder 
This was originally thrown out since it was slow and cost too much
resources. Due to other changes in the core, it is now cheaper
than the other one
 2019-10-29 21:54:22 +01:00
Olof Kindgren
574464a33b De-pipeline alu_result_sel 2019-10-29 21:53:13 +01:00
Olof Kindgren
2b5c71fe9b Gate mem_rd in mem_if 2019-09-26 23:31:23 +02:00
Olof Kindgren
7bd89deb41 Simplify mret/csr address generation 2019-09-26 23:09:22 +02:00
Olof Kindgren
bad823ff6d Fix syntax error for o_take_branch 2019-09-26 22:59:46 +02:00
Olof Kindgren
5a44634ee5 Avoid exposing funct3 from decode 2019-09-15 23:50:02 +02:00
Olof Kindgren
9575eb4fef Separate decode and state 2019-09-15 23:25:10 +02:00
Olof Kindgren
7289a68f6e Separate state from o_bufreg_loop 2019-09-14 22:52:41 +02:00
Olof Kindgren
c0a177aebe Simplify o_alu_cmp_uns 2019-09-14 22:21:25 +02:00
Olof Kindgren
1248043a39 Separate state and decode from CSR signals 2019-09-14 22:18:03 +02:00
Olof Kindgren
ef3fc9274d Rename misleading signal names 2019-09-13 23:30:46 +02:00
Olof Kindgren
8dc137fb07 Kill of mem_init and mem_en 2019-09-13 23:30:46 +02:00
Olof Kindgren
e20e0eef8f Optimize dbus_cyc 2019-09-13 23:30:46 +02:00
Olof Kindgren
a0ba84096a Simplify csr stuff 2019-09-13 23:30:46 +02:00
Olof Kindgren
7425128dd8 Pass imm offsets through bufreg 2019-09-13 23:30:46 +02:00
Olof Kindgren
d2cf7e547a Interrupt refactoring 2019-08-25 22:47:29 +02:00
Olof Kindgren
fb7c6c1458 Simplify csr_en logic 2019-07-23 12:10:38 +02:00