924 commits

Author	SHA1	Message	Date
Blaise Tine	3f5fd6d394	using shiftreg-based skid buffers	2021-02-28 02:20:09 -08:00
Blaise Tine	e64996946d	using 44-bit perf counters - aligned with DSP counters width	2021-02-28 02:05:47 -08:00
Blaise Tine	8a9a67aa5a	minor update	2021-02-27 21:54:55 -08:00
Blaise Tine	f5a17bd1a9	decode optimization and refactoring	2021-02-27 18:21:41 -08:00
Blaise Tine	ebee332e9d	minor update	2021-02-27 02:31:05 -08:00
Blaise Tine	20d704b4d3	skid buffer optimization	2021-02-27 02:29:48 -08:00
Blaise Tine	34ce0b8e89	minor update	2021-02-23 20:54:03 -08:00
Blaise Tine	700f9eea19	moving MUL unit into ALU unit	2021-02-23 13:49:02 -08:00
Blaise Tine	1792571e1b	minor update	2021-02-22 13:30:45 -08:00
Blaise Tine	1346d64ba9	minor update	2021-02-22 04:04:13 -08:00
Blaise Tine	7560202f8b	cache bank refactoring - removing unecessary core response fifo & restoring single port data access	2021-02-21 21:47:46 -08:00
Blaise Tine	ccb74ef286	cache data access with decoupled read/write ports	2021-02-21 15:18:24 -08:00
Blaise Tine	3e961c4e6e	minor update	2021-02-21 15:14:46 -08:00
Blaise Tine	6739dc7923	minor update - registering execute units skid buffers	2021-02-21 15:11:08 -08:00
Blaise Tine	f27c1fac5f	minor update	2021-02-21 03:38:24 -08:00
Blaise Tine	6d7692da37	minor fix.	2021-02-21 03:37:36 -08:00
Blaise Tine	258eb633a6	minor update	2021-02-20 13:16:25 -08:00
Blaise Tine	05f93fac20	minor update	2021-02-20 13:15:15 -08:00
Blaise Tine	143319d557	minor optimization	2021-02-18 16:03:16 -08:00
Blaise Tine	31b3e380dc	minor update	2021-02-15 09:23:40 -08:00
Blaise Tine	9eed48435c	instruction decode optimization	2021-02-14 00:19:54 -08:00
Blaise Tine	3c37db877a	cache specialization for in-order DRAM reponses	2021-02-13 20:23:29 -08:00
Blaise Tine	073964fdf7	minor update	2021-02-12 08:52:06 -08:00
Blaise Tine	ab63ac9e5d	cache request interfaces update	2021-02-10 20:55:04 -08:00
Blaise Tine	665b97b810	multi-ported cache support for streaming	2021-02-08 16:13:32 -08:00
Blaise Tine	fd1726197b	cache merge optimization	2021-02-07 07:33:39 -08:00
Blaise Tine	6c1dc96626	simX refactoring + removed oldRTL + CSR updates	2021-02-06 12:52:54 -08:00
Blaise Tine	111cc29482	minor update	2021-02-04 15:28:04 -08:00
Blaise Tine	72b6713a72	updating fdiv/fsqrt bram hex files, reset_delay updaet	2021-02-04 09:02:18 -08:00
Blaise Tine	32b94f61f2	minor update	2021-02-01 11:00:09 -08:00
Blaise Tine	62ff97d6e1	minor update - smem perf update	2021-02-01 10:29:20 -08:00
Blaise Tine	dc18bfabb8	minor update - remove mshr data store	2021-01-30 06:40:48 -08:00
Blaise Tine	de2e118cc2	move opae to /hw/syn/	2021-01-25 02:32:49 -08:00
Blaise Tine	5419859281	fcvt fix	2021-01-25 02:22:00 -08:00
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	74a687e395	minor updates	2021-01-18 05:43:30 -08:00
Blaise Tine	b17f1109c6	minor updates	2021-01-18 04:34:34 -08:00
Blaise Tine	ce9ef840d6	minor updates	2021-01-18 04:22:40 -08:00
Blaise Tine	9bce15a513	minor updates	2021-01-17 18:20:02 -08:00
Blaise Tine	a7f6b9fffc	minor updates	2021-01-17 18:18:05 -08:00
Blaise Tine	1237a72536	minor updates	2021-01-17 18:11:42 -08:00
Blaise Tine	8b42393189	minor updates	2021-01-17 17:33:41 -08:00
Blaise Tine	a046bd7a73	cache pipeline optimization	2021-01-17 17:19:52 -08:00
Blaise Tine	ed216ab39d	minor updates	2021-01-17 13:58:43 -08:00
Blaise Tine	98945df5ae	minor updates	2021-01-17 12:50:07 -08:00
Blaise Tine	a69ba5ad7b	cache flush support	2021-01-17 05:50:29 -08:00
Blaise Tine	d4e7b28be8	cache refactoring	2021-01-17 00:18:56 -08:00
Blaise Tine	5b80484123	minor updates	2021-01-16 14:16:10 -08:00
Blaise Tine	a56ecb696d	minor updates	2021-01-16 14:05:47 -08:00
Blaise Tine	4f26228d50	minor updates	2021-01-16 05:33:28 -08:00