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3193 commits 27 branches 9 tags 1.6 GiB
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49 commits

Author SHA1 Message Date
MichaelJSr
0d04423074 Readded the ecall and ebreak instruction traps so that the riscv-vector tests run properly 2024-10-14 10:12:33 -07:00
jaewon-lee-github
d1175a03c9 update the code accessing registers in obsoleted way 2024-10-02 14:16:57 -04:00
Jaewon Lee
4a606061d2
Merge branch 'develop' into tensor-core 2024-09-30 16:48:47 -04:00
Blaise Tine
a38960674e SimX split.N fix 2024-08-28 21:10:05 -07:00
Blaise Tine
41e41c9688 adjust SimX's split/join to match RTL. 2024-08-28 18:46:30 -07:00
Blaise Tine
2bc8a881b6 fixed trace log formatting 2024-07-30 12:05:36 -07:00
Blaise Tine
a2307a28dc perf counters update 2024-07-12 19:02:43 -07:00
Blaise Tine
42f3d55e15 SimX operands collector optimization 2024-07-12 04:54:44 -07:00
Blaise Tine
3efced37c5 trace INSTANCE_ID refactoring 2024-07-09 13:33:17 -07:00
Nayan Sivakumar Nair
5b0fc8cbd4 Fixes for PR 2024-06-25 03:18:50 -04:00
Nayan Sivakumar Nair
a378aed67c Moved tc_num, tc_size param to makefile args 2024-06-21 22:23:24 -04:00
Varsha Singhania
0e3badf723 Script checkin and code cleanup 2024-06-18 02:19:57 -04:00
Varsha Singhania
99c6a1af5a Tensor cores in Vortex 2024-06-17 04:28:51 -04:00
Blaise Tine
5bcf24ed55 64-bit rtl fix 2024-06-13 06:26:45 -07:00
Blaise Tine
f8ef570778 riscv tests refactoring 2024-05-28 10:46:31 -07:00
Blaise Tine
e1c8ff02be minor update 2024-05-21 12:46:15 -07:00
Blaise Tine
210e4a8e8f minor update 2024-05-21 12:45:03 -07:00
Blaise Tine
9b79d60507 minor update 2024-05-21 05:39:35 -07:00
Blaise Tine
b3f96e288a + support for ZICOND RISC-V extension 
+ RTL decode refactoring
 2024-05-20 00:17:24 -07:00
Blaise Tine
b5ca7a999c SIMT stack fix 2024-05-01 20:50:21 -07:00
Blaise Tine
4737cdabbd minor update 2024-05-01 08:06:45 -07:00
Blaise Tine
ca79e69355 SIMT Tack compression 2024-04-30 02:19:32 -07:00
Blaise Tine
a167c07e7d adding wait cycles to wspawn 2024-04-28 04:27:47 -07:00
Blaise Tine
db35f5d768 simx decode bug fix. 2024-04-09 01:34:14 -07:00
Blaise Tine
840ced22a9 simx refactoring - emulation vs simulation discrete separation 2024-03-12 00:23:42 -07:00
Blaise Tine
ff6f33acff simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_ 2024-03-11 15:39:49 -07:00
Blaise Tine
041f573815 cleaned up vector code from simx 2024-02-21 18:27:52 -08:00
Blaise Tine
b0b7cd2b1e minor updates 2024-02-03 19:09:53 -08:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Blaise Tine
d297351211 simx64 bug fix 2022-02-05 17:13:16 -05:00
Blaise Tine
bda77760c8 addition bug fixes 2022-02-05 09:14:35 -05:00
Blaise Tine
5fbace9fa0 fixed several bugs and refactor memory access 2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Santosh Srivatsan
836c777680 XLEN parameterization for simx 2022-02-03 15:19:31 -05:00
Santosh Srivatsan
7e3a2fdb0f Modifications to allow 64-bit riscv tests to run on travis CI 2022-01-27 15:55:19 -05:00
Santosh Srivatsan
7aa93a735d Added FLEN parameterization for RV32/64 F and D instructions 2022-01-24 15:42:15 -05:00
Santosh Srivatsan
ad92c09f5b Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile 2022-01-22 13:47:44 -05:00
Santosh Srivatsan
91c22a2592 Fixed some riscv-tests 2022-01-22 12:54:10 -05:00
Santosh Srivatsan
f93303bac7 Minor update 2021-12-15 17:21:38 -05:00
Santosh Srivatsan
4abfca4cb2 Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI 2021-12-13 19:55:02 -05:00
Santosh Srivatsan
e82d5fe48f Removed all comments labelled \'simx64\' 2021-12-13 19:52:13 -05:00
Santosh Srivatsan
67daa6e616 Minor update 2021-12-11 17:58:31 -05:00
Santosh Srivatsan
885bb58ca9 Merged RV64IMFD extensions to master branch 2021-12-11 17:06:29 -05:00
Santosh Srivatsan
5edb9098ce Merge branch 'simx64' 2021-12-10 21:48:29 -05:00
Santosh Srivatsan
e7bc436b52 Renamed simX to simx 2021-12-10 16:57:29 -05:00
Blaise Tine
0e2de4f13a prefetch test fixes 2021-12-09 04:54:10 -05:00
Blaise Tine
5825b7c15a dram simulator fix 2021-12-07 22:44:06 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
2a7a4df342 simx directory name fix 2021-11-30 07:17:58 -05:00
Renamed from sim/simX/execute.cpp (Browse further)