709 commits

Author	SHA1	Message	Date
Blaise Tine	b930a822ad	minor updates	2020-05-28 18:34:03 -04:00
Blaise Tine	611ceb000a	fixed warp_sched lock bug	2020-05-28 08:52:20 -04:00
Blaise Tine	9e5885b820	adding dram writeenable support + scheduler bug fixes	2020-05-27 19:00:23 -04:00
Blaise Tine	61231cd2af	OPAE rtl fixes	2020-05-24 02:42:56 -07:00
Blaise Tine	a9f896b4f3	fixed snoop forwarding bug and single bank support	2020-05-24 04:29:43 -04:00
Blaise Tine	47ed6b18ff	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-05-24 01:37:55 -04:00
felsabbagh3	a1e9b512b0	Added mrvq_recover_ready_state_st2 to optimize fills sent	2020-05-23 21:47:51 -07:00
felsabbagh3	0cd9bd689e	Added schedule_ptr to mrvq for speculative pops	2020-05-23 21:36:57 -07:00
Blaise Tine	3a9e79d979	revert byte_enable tag structure	2020-05-23 22:23:25 -04:00
Blaise Tine	c54fa50715	fixed snoop forwarder dequue to support out of order responses	2020-05-23 20:19:54 -04:00
Blaise Tine	507622f1a1	fixed simulator snoop handling	2020-05-23 19:26:59 -04:00
Blaise Tine	6882d88a62	removed fill_invalidator (not needed anymore)	2020-05-23 19:24:52 -04:00
Blaise Tine	f3b21aab8f	remove unsued cache parameter LLVQ_SIZE	2020-05-23 00:33:51 -04:00
Blaise Tine	70dadca9fe	fix scheduler rename_table X values - reverted valid bits	2020-05-23 00:22:56 -04:00
Blaise Tine	b02fc14da6	fill invalifator fix + refactoring	2020-05-21 20:38:55 -07:00
Blaise Tine	70c70407c9	minor update	2020-05-21 12:08:16 -07:00
Blaise Tine	3c8620e770	minor update	2020-05-21 14:51:56 -04:00
Blaise Tine	cf22ef2bf3	minor update	2020-05-21 13:42:08 -04:00
Blaise Tine	d12c40131e	optimize generic_queue to support simple model for smaller size queues	2020-05-21 04:04:27 -04:00
Blaise Tine	276fa5c919	optimize generic_queue to support simple model for smaller size queues	2020-05-21 03:34:03 -04:00
felsabbagh3	7e091b53f8	Added valid_table in scheduler and removed rename_table on reset	2020-05-20 23:02:41 -07:00
Blaise Tine	1102871180	force random values for unitialized signals	2020-05-20 20:57:15 -04:00
Blaise Tine	7e5fed3ec1	Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis	2020-05-20 18:27:20 -04:00
Blaise Tine	d4cb8b6f66	fixed renaem table reset logic	2020-05-20 18:24:09 -04:00
Blaise Tine	72d54c749c	fixed cache msrq reset logic	2020-05-20 18:11:31 -04:00
Blaise Tine	e1b4862f85	minor update	2020-05-20 14:14:29 -07:00
Blaise Tine	cefd0d85af	rtl refactoring	2020-05-20 16:59:14 -04:00
Blaise Tine	b5569dd525	OPAE rtl fixes	2020-05-20 12:08:10 -07:00
felsabbagh3	cad92bbeb1	Qualify scheduler_delay with valid signal	2020-05-19 14:59:17 -07:00
Blaise Tine	c209d902a3	update	2020-05-19 17:41:51 -04:00
Blaise Tine	e269909db9	opae rtl fixes	2020-05-19 13:47:47 -07:00
Blaise Tine	0c88da2bfb	opae rtl fixes	2020-05-18 20:19:02 -07:00
Blaise Tine	11ace25f27	opae rtl fixes	2020-05-17 20:29:42 -07:00
felsabbagh3	26f9fc96c3	Corner case where the pipeline is stalled, makes mrvq entereis valid, but when unstalled mrvq_init isn't set up correctly	2020-05-16 21:20:57 -07:00
felsabbagh3	101de6b138	mrvq update ready + init ready as 1 in same cycle causing incorrect ready state	2020-05-16 18:52:30 -07:00
felsabbagh3	4bf0bcca8a	Fix incorrect CSR forwarding for GID between different warps	2020-05-16 17:56:15 -07:00
felsabbagh3	e2741f9cdb	Force miss_add init ready to 1 when core req matches with mrvq entry, regardless of hit/miss	2020-05-16 16:26:26 -07:00
Blaise Tine	d6c87dbb0a	added debug print states or rtl	2020-05-16 14:19:17 -04:00
Blaise Tine	65c2da76cf	snooping response handling fix	2020-05-14 23:34:52 -04:00
Blaise Tine	57a037b2f4	snooping response handling fix	2020-05-14 23:06:15 -04:00
Blaise Tine	d623ef4029	snooping response handling fix	2020-05-14 23:05:46 -04:00
Blaise Tine	bcb9514799	snooping response handling fix	2020-05-14 11:01:41 -04:00
felsabbagh3	ff140b6811	Added an initial ready state to an mrvq entry that might be set to 1	2020-05-12 21:47:51 -07:00
felsabbagh3	5b2624046e	Avoid snoop deadlock whith snoops. Adds mrvq not almost full for snrq pop	2020-05-12 21:30:17 -07:00
felsabbagh3	b08b80156d	Added pending request check. This applies when 1) mrvq entery is valid/ready but not head, then a core request hits 2) snoop when pending write. A pending miss request is either a valid entry in mrvq OR a miss entery in st2	2020-05-12 21:25:13 -07:00
Blaise Tine	b0b38f6c24	snooping response handling fix	2020-05-12 18:52:24 -04:00
Blaise Tine	fcf3800d5d	snooping response handling fix	2020-05-12 13:35:18 -04:00
Blaise Tine	c49f01b769	snooping response handling	2020-05-11 22:55:44 -04:00
Blaise Tine	b6c4aa0baa	rtl refactoring	2020-05-10 09:52:38 -04:00
Blaise Tine	cc84e0691c	multicore fix	2020-05-10 08:30:04 -04:00