tinebp
e80ee2c819
minor update
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2025-01-22 04:56:49 -08:00
MichaelJSr
6d27575db3
Revert some of "Added ifndef statements for the vector extension anywhere they didn't exist already"
2025-01-14 21:56:39 -08:00
MichaelJSr
a2cfeffcfe
Added ifndef statements for the vector extension anywhere they didn't exist already
...
Added ifndef statements for the vector extension anywhere they didn't exist already
more ifdef statements
more ifdef
Update decode.cpp
Update decode.cpp
Update decode.cpp
2025-01-14 21:29:47 -08:00
tinebp
6b23d290c3
vector ISA updates
2024-12-05 14:43:51 -08:00
MichaelJSr
073e0ddd10
Adds the riscv vector extension into simx
...
Added vector regression test to ci.yml
2024-11-27 23:22:22 -08:00
Jaewon Lee
4a606061d2
Merge branch 'develop' into tensor-core
2024-09-30 16:48:47 -04:00
Blaise Tine
a38960674e
SimX split.N fix
2024-08-28 21:10:05 -07:00
Blaise Tine
0f41774fea
SimX's decode minor fix
2024-08-28 19:07:15 -07:00
Blaise Tine
2bc8a881b6
fixed trace log formatting
2024-07-30 12:05:36 -07:00
Blaise Tine
578c3d33d2
cumulative fixes
2024-07-15 10:13:57 -07:00
Nayan Sivakumar Nair
5b0fc8cbd4
Fixes for PR
2024-06-25 03:18:50 -04:00
Varsha Singhania
99c6a1af5a
Tensor cores in Vortex
2024-06-17 04:28:51 -04:00
Blaise Tine
b3f96e288a
+ support for ZICOND RISC-V extension
...
+ RTL decode refactoring
2024-05-20 00:17:24 -07:00
Blaise Tine
4737cdabbd
minor update
2024-05-01 08:06:45 -07:00
Blaise Tine
ca79e69355
SIMT Tack compression
2024-04-30 02:19:32 -07:00
Blaise Tine
135cc4f5a7
minor update
2024-04-09 01:58:04 -07:00
Blaise Tine
840ced22a9
simx refactoring - emulation vs simulation discrete separation
2024-03-12 00:23:42 -07:00
Blaise Tine
041f573815
cleaned up vector code from simx
2024-02-21 18:27:52 -08:00
Blaise Tine
970cbf066a
cleanup
2023-11-03 08:09:59 -04:00
Blaise Tine
65ca0fff3a
minor update
2023-10-20 00:48:05 -07:00
Blaise Tine
d47cccc157
Vortex 2.0 changes:
...
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
2023-10-19 20:51:22 -07:00
Blaise Tine
1bd25acb0b
cmov
2022-02-05 17:58:12 -05:00
Santosh Srivatsan
b7e5a83ba3
Merged branch xlen-parameterization into staging
2022-02-05 13:47:42 -05:00
Blaise Tine
140124b423
additional bug fixes
2022-02-05 07:42:50 -05:00
Blaise Tine
703d3faf27
minor bug fixes
2022-02-05 06:37:54 -05:00
Blaise Tine
5fbace9fa0
fixed several bugs and refactor memory access
2022-02-04 17:50:19 -05:00
Blaise Tine
cf2a0a5f39
code refactoring
2022-02-04 00:07:24 -05:00
Santosh Srivatsan
836c777680
XLEN parameterization for simx
2022-02-03 15:19:31 -05:00
Santosh Srivatsan
7e3a2fdb0f
Modifications to allow 64-bit riscv tests to run on travis CI
2022-01-27 15:55:19 -05:00
Santosh Srivatsan
7aa93a735d
Added FLEN parameterization for RV32/64 F and D instructions
2022-01-24 15:42:15 -05:00
Santosh Srivatsan
ad92c09f5b
Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile
2022-01-22 13:47:44 -05:00
Santosh Srivatsan
91c22a2592
Fixed some riscv-tests
2022-01-22 12:54:10 -05:00
Blaise Tine
29df0da8b5
minor warning fixes
2022-01-10 20:33:37 -05:00
Santosh Srivatsan
71acf4eadb
Changed instruction size from wsize() * 4 to wsize() * 8
2021-12-13 20:42:44 -05:00
Santosh Srivatsan
4abfca4cb2
Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI
2021-12-13 19:55:02 -05:00
Santosh Srivatsan
e82d5fe48f
Removed all comments labelled \'simx64\'
2021-12-13 19:52:13 -05:00
Santosh Srivatsan
885bb58ca9
Merged RV64IMFD extensions to master branch
2021-12-11 17:06:29 -05:00
Santosh Srivatsan
5edb9098ce
Merge branch 'simx64'
2021-12-10 21:48:29 -05:00
Santosh Srivatsan
e7bc436b52
Renamed simX to simx
2021-12-10 16:57:29 -05:00
Blaise Tine
0e2de4f13a
prefetch test fixes
2021-12-09 04:54:10 -05:00
Blaise Tine
2a7a4df342
simx directory name fix
2021-11-30 07:17:58 -05:00
