130 commits

Author	SHA1	Message	Date
Blaise Tine	bde6a69ea0	adding support for multi-banks memory bus	2021-05-04 07:32:03 -07:00
Blaise Tine	bac53e4ae1	minor update	2021-05-02 11:05:49 -07:00
Blaise Tine	e40a3feefa	minor update	2021-05-01 10:33:24 -07:00
Blaise Tine	d504adb236	afu mem controller refactoring	2021-05-01 08:39:52 -07:00
Blaise Tine	95f057bc2e	fpga build refactoring	2021-04-29 06:17:28 -07:00
Blaise Tine	64848788a1	minor update	2021-04-26 20:34:28 -07:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	cad21a4b92	minor update	2021-04-24 01:17:38 -04:00
Blaise Tine	4cb98a25a7	enabling 128-bit dram bus	2021-04-24 00:31:27 -04:00
Blaise Tine	e85fa9d842	fixed FCVT timing critical path	2021-03-18 13:26:36 -07:00
Blaise Tine	062d02ddce	Merge branch 'master' of https://github.gatech.edu/casl/Vortex	2021-03-04 20:51:03 -08:00
Blaise Tine	8775f63ec4	lkg build rollout with 16cores optimization on arria10	2021-01-24 16:49:22 -08:00
Blaise Tine	ed216ab39d	minor updates	2021-01-17 13:58:43 -08:00
Blaise Tine	fe64c47f60	ccip write fix	2021-01-14 22:49:06 -08:00
Blaise Tine	79cc4d98e6	bank deadlock fix	2021-01-13 13:06:07 -08:00
Blaise Tine	464c4f4bd8	minor updates	2021-01-12 20:16:59 -08:00
Blaise Tine	f18ac24675	afu reset fix	2021-01-12 17:13:47 -08:00
Blaise Tine	e770824d47	fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance	2021-01-10 20:26:15 -08:00
Blaise Tine	06945533cf	fixed l2/l3 caches related bugs	2021-01-09 16:32:55 -08:00
Blaise Tine	ba1082249a	minor update	2021-01-06 23:30:30 -08:00
Blaise Tine	2b8435471a	speeding up simulation using dedicated full dpi-based FPU core	2021-01-06 18:44:06 -08:00
Blaise Tine	762b8e2e3e	fixed cache mshr critical path	2021-01-04 12:49:40 -05:00
Blaise Tine	4bc3b537bd	fixed reset fan-out	2021-01-03 20:06:36 -08:00
Blaise Tine	d44144f72f	FPU float<->int conversion optimization	2020-12-29 15:37:45 -08:00
Blaise Tine	33c431ed44	multiplier unit optimization - using fifo for metadata, shift register optimization	2020-12-26 11:23:21 -08:00
Blaise Tine	703a861fe9	added support for write-through cache, removed cache snooping support	2020-12-23 23:51:02 -08:00
Blaise Tine	4b7d871d62	allowing partial cache request submissions, io bus support broken	2020-12-21 03:53:13 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	12f7fcfa75	adding missing files, buffering teh snoop forwarder	2020-12-09 00:24:32 -08:00
Blaise Tine	14baec86d5	moved apae sources into rtl/afu	2020-12-08 04:59:11 -08:00