87 commits

Author	SHA1	Message	Date
Blaise Tine	f68af3bb84	using mshr pending request size	2020-12-01 00:54:25 -08:00
Blaise Tine	97739e9dcf	RAM blocks inference fixes	2020-11-30 14:02:47 -08:00
Blaise Tine	e6466b887c	minor update	2020-10-20 08:45:21 -07:00
Blaise Tine	7529f72c5d	fixed OPAE crash, added custom bram module to controll rw collision, dogfood testcase argurment, optimzed buffered fifo, quartus build optimization flags	2020-10-20 05:32:55 -07:00
Blaise Tine	32da50816f	scope refactoring: adding modules definitions to VCD trace	2020-10-12 23:26:02 -04:00
Blaise Tine	0a45a8beb3	minor update	2020-09-01 00:56:10 -07:00
Blaise Tine	fde3f46798	ibuffer optimization	2020-08-26 04:44:36 -07:00
Blaise Tine	f292e5003d	quartus build fixes	2020-08-23 22:04:46 -07:00
Blaise Tine	1c9445745f	fp_noncomp fixes	2020-08-23 16:53:28 -07:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	6c12391338	pipeline refactoring - fmax >= 222 mhz	2020-08-14 21:50:14 -07:00
Blaise Tine	cd29362d10	fixed FPU handshake, optimized writeback's critical path	2020-08-07 10:11:54 -07:00
Blaise Tine	ffd9515881	added altera fpu modules	2020-08-05 15:53:59 -07:00
Blaise Tine	836a735555	minor updates	2020-07-31 13:39:52 -07:00
Blaise Tine	c2dd0a8b39	modelsim fixes && pipeline optimization	2020-07-28 14:20:23 -07:00
Blaise Tine	bdfacf709c	yosys synthesis refactoring	2020-07-10 18:56:41 -04:00
Blaise Tine	f66c251309	minor update	2020-06-29 15:09:14 -07:00
Blaise Tine	f0046fed3c	added synthesis for Vortex single core	2020-06-29 08:39:57 -07:00
Blaise Tine	a70562d386	set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18	2020-06-29 08:03:19 -07:00
Blaise Tine	21e04a0cb0	minor update	2020-06-28 22:58:18 -07:00
Blaise Tine	5e718c2676	refactoring	2020-06-23 09:54:40 -07:00
Blaise Tine	e6bbf671ee	minor update	2020-06-20 15:25:21 -07:00
Blaise Tine	68d9fc9a75	driver basic test and demo test refactoring	2020-06-19 09:12:07 -07:00
Blaise Tine	e2e1b63e14	refactor synthesis scripts + fixed quartus ram read-after-write bypass	2020-06-16 11:45:47 -07:00
Blaise Tine	457783322b	scope fixes	2020-06-09 07:03:52 -07:00
Blaise Tine	04fc34b848	minor update	2020-06-03 03:05:45 -07:00
Blaise Tine	16d5a8a09c	opae rtl fixes	2020-05-31 14:51:42 -07:00
Blaise Tine	1512138a15	minor update	2020-05-22 19:14:07 -07:00
Blaise Tine	b02fc14da6	fill invalifator fix + refactoring	2020-05-21 20:38:55 -07:00
Blaise Tine	f53256f854	quartus projects	2020-04-21 12:28:37 -07:00
Blaise Tine	cb0afd3eec	fix quartus build	2020-04-21 00:55:18 -07:00
Blaise Tine	07d308d2ce	update	2020-04-21 02:41:37 -04:00
Blaise Tine	a0e15af0dc	RTL code refactoring	2020-04-20 13:01:42 -04:00
Blaise Tine	e8a4923eb4	RTL code refactoring	2020-04-20 12:09:30 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00
Blaise Tine	22c8da7490	renamed Vortex_SOC to Vortex_Socket	2020-04-14 08:33:32 -04:00
Blaise Tine	fc155e1223	project directories reorganization	2020-04-14 06:35:20 -04:00