github-mirrors
Your window into the Elastic Stack
Updated 2026-05-09 08:49:24 -06:00
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asip
axi
cpu
embedded
fpga
microcontroller
neorv32
on-chip-debbuger
processor
risc-v
riscv
rtl
rtos
rv32
safety
soc
soft-core
system-on-chip
verilog
vhdl
Updated 2026-05-09 01:32:06 -06:00
A browser based Pokémon fangame heavily inspired by the roguelite genre.
Updated 2026-05-08 19:01:21 -06:00
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Updated 2026-05-08 08:48:06 -06:00
Base images for Immich containers
Updated 2026-05-07 13:12:48 -06:00
Helm chart implementation of Immich
Updated 2026-05-07 08:50:17 -06:00
Docker image for Prowlarr/Prowlarr
Updated 2026-05-06 00:21:50 -06:00
Self-hosted audiobook and podcast server
Updated 2026-05-05 16:18:49 -06:00