cva5/core
2022-01-18 11:29:35 -08:00
..
div_algorithms linting : div interface parameter changes 2020-06-22 15:20:19 -07:00
intel packaging updates 2019-09-08 10:48:35 -07:00
xilinx Added missing import statement. 2020-07-27 15:36:10 -07:00
alu_unit.sv alu done moved off of critical path 2020-06-05 10:47:58 -07:00
amo_alu.sv DDR simulation 2020-06-03 20:39:35 +00:00
avalon_master.sv code cleanups 2020-01-22 19:59:33 -08:00
axi_master.sv code cleanup: converted set/clr register usage into a module 2020-04-02 15:32:02 -07:00
axi_to_arb.sv Added L2 arbiter to verilator test platform 2020-03-05 15:00:36 -08:00
barrel_shifter.sv code cleanups 2020-01-22 19:59:33 -08:00
binary_occupancy.sv FIFO cleanups 2019-08-20 22:07:53 -07:00
branch_comparator.sv initial ID rework for processor front end 2020-06-03 13:49:50 -07:00
branch_predictor.sv cleaning up repo 2022-01-18 11:29:35 -08:00
branch_predictor_ram.sv cleaning up repo 2022-01-18 11:29:35 -08:00
branch_unit.sv bug fixes 2020-06-16 16:48:27 -07:00
byte_en_BRAM.sv Added missing import statement. 2020-07-23 16:27:08 -07:00
clz.sv quick div performance improvements 2018-12-17 22:05:34 -08:00
csr_regs.sv TLB updates 2022-01-18 11:29:35 -08:00
csr_types.sv privilege updates 2020-04-07 16:17:51 -07:00
cycler.sv code cleanup 2018-06-11 15:24:22 -07:00
dbram.sv changed l/s unit muxing 2019-09-25 13:56:38 -07:00
dcache.sv cleaning up repo 2022-01-18 11:29:35 -08:00
ddata_bank.sv Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
decode_and_issue.sv fetch mmu fault propagation 2022-01-18 11:29:35 -08:00
div_unit.sv cleaning up repo 2022-01-18 11:29:35 -08:00
div_unit_core_wrapper.sv div commit 2019-10-21 16:24:44 -07:00
dtag_banks.sv cleaning up repo 2022-01-18 11:29:35 -08:00
external_interfaces.sv cleaning up repo 2022-01-18 11:29:35 -08:00
fetch.sv fetch mmu fault propagation 2022-01-18 11:29:35 -08:00
gc_unit.sv TLB updates 2022-01-18 11:29:35 -08:00
ibram.sv fetch cleanups and reduced branch flush fanout 2019-09-27 15:58:49 -07:00
icache.sv cleaning up repo 2022-01-18 11:29:35 -08:00
id_inuse.sv execution and writeback changes for new ID system 2020-06-03 13:50:20 -07:00
illegal_instruction_checker.sv basic illegal instruction support 2020-05-07 16:41:35 -07:00
instruction_metadata_and_id_management.sv fetch mmu fault propagation 2022-01-18 11:29:35 -08:00
interfaces.sv TLB updates 2022-01-18 11:29:35 -08:00
itag_banks.sv tag range reductions 2020-01-21 19:07:55 -08:00
l1_arbiter.sv l1arb cleanup 2020-06-30 11:04:00 -07:00
load_store_queue.sv bug fixes 2020-06-16 16:48:27 -07:00
load_store_unit.sv TLB updates 2022-01-18 11:29:35 -08:00
lut_ram.sv paramaterized read ports on basic LUTRAM block 2020-06-03 13:50:20 -07:00
mmu.sv added support to abort MMU requests 2022-01-18 11:29:35 -08:00
msb.sv final changes for verilator support 2018-12-19 12:04:48 -08:00
msb_naive.sv changes for vivado simulation 2019-09-03 16:48:58 -07:00
mstatus_priv_reg.sv changes for verilator support 2018-11-29 13:44:33 -08:00
mul_unit.sv bug fixes 2020-06-16 16:48:27 -07:00
one_hot_occupancy.sv trimmed two_plus output 2019-08-21 13:12:25 -07:00
one_hot_to_integer.sv execution and writeback changes for new ID system 2020-06-03 13:50:20 -07:00
placer_randomizer.sv helper for placement randomization 2019-01-03 12:39:09 -08:00
ras.sv RAS improvements 2020-06-09 11:01:21 -07:00
reg_inuse.sv code cleanups 2020-01-22 19:59:33 -08:00
regfile_bank_sel.sv regfile fix 2020-06-07 20:27:51 -07:00
register_file.sv parameterized number of read ports on regfile 2020-06-07 14:07:33 -07:00
register_file_and_writeback.sv added invalid fetch propagation and dedicated commit port zero to the ALU 2020-06-29 17:35:24 -07:00
riscv_types.sv Added support for additional CSRs 2022-01-18 11:29:35 -08:00
set_clr_reg_with_rst.sv code cleanup: converted set/clr register usage into a module 2020-04-02 15:32:02 -07:00
shift_counter.sv cleaning up repo 2022-01-18 11:29:35 -08:00
tag_bank.sv minor cleanups 2020-06-30 11:06:07 -07:00
taiga.sv fetch mmu fault propagation 2022-01-18 11:29:35 -08:00
taiga_config.sv Changed localparam to parameters to satify IP packager requirements. 2020-07-27 14:27:46 -07:00
taiga_fifo.sv fifo improvements 2020-06-30 11:25:10 -07:00
taiga_types.sv fetch mmu fault propagation 2022-01-18 11:29:35 -08:00
tlb_lut_ram.sv TLB updates 2022-01-18 11:29:35 -08:00
toggle_memory.sv in-flight reset support 2020-06-26 16:37:59 -07:00
wishbone_master.sv code cleanup: converted set/clr register usage into a module 2020-04-02 15:32:02 -07:00