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div_algorithms
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linting : div interface parameter changes
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2020-06-22 15:20:19 -07:00 |
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intel
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packaging updates
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2019-09-08 10:48:35 -07:00 |
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xilinx
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Added missing import statement.
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2020-07-27 15:36:10 -07:00 |
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addr_hash.sv
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addr hash typo fix
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2022-01-18 11:29:35 -08:00 |
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alu_unit.sv
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alu done moved off of critical path
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2020-06-05 10:47:58 -07:00 |
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amo_alu.sv
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DDR simulation
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2020-06-03 20:39:35 +00:00 |
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avalon_master.sv
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code cleanups
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2020-01-22 19:59:33 -08:00 |
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axi_master.sv
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code cleanup: converted set/clr register usage into a module
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2020-04-02 15:32:02 -07:00 |
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axi_to_arb.sv
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Added L2 arbiter to verilator test platform
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2020-03-05 15:00:36 -08:00 |
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barrel_shifter.sv
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code cleanups
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2020-01-22 19:59:33 -08:00 |
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binary_occupancy.sv
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FIFO cleanups
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2019-08-20 22:07:53 -07:00 |
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branch_comparator.sv
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initial ID rework for processor front end
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2020-06-03 13:49:50 -07:00 |
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branch_predictor.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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branch_predictor_ram.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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branch_unit.sv
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bug fixes
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2020-06-16 16:48:27 -07:00 |
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byte_en_BRAM.sv
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Added missing import statement.
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2020-07-23 16:27:08 -07:00 |
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clz.sv
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quick div performance improvements
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2018-12-17 22:05:34 -08:00 |
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csr_regs.sv
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TLB updates
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2022-01-18 11:29:35 -08:00 |
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csr_types.sv
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privilege updates
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2020-04-07 16:17:51 -07:00 |
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cycler.sv
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code cleanup
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2018-06-11 15:24:22 -07:00 |
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dbram.sv
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changed l/s unit muxing
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2019-09-25 13:56:38 -07:00 |
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dcache.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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ddata_bank.sv
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Edited file header and error msg for DIV, MUL, and ALU
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2018-06-05 12:54:42 -07:00 |
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decode_and_issue.sv
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CSR read separated from LS path
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2022-01-18 11:29:35 -08:00 |
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div_unit.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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div_unit_core_wrapper.sv
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div commit
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2019-10-21 16:24:44 -07:00 |
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dtag_banks.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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external_interfaces.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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fetch.sv
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RAS changes for early branch correction
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2022-01-18 11:29:35 -08:00 |
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gc_unit.sv
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CSR read separated from LS path
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2022-01-18 11:29:35 -08:00 |
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ibram.sv
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fetch cleanups and reduced branch flush fanout
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2019-09-27 15:58:49 -07:00 |
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icache.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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id_inuse.sv
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execution and writeback changes for new ID system
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2020-06-03 13:50:20 -07:00 |
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illegal_instruction_checker.sv
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basic illegal instruction support
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2020-05-07 16:41:35 -07:00 |
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instruction_metadata_and_id_management.sv
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RAS changes for early branch correction
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2022-01-18 11:29:35 -08:00 |
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interfaces.sv
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TLB updates
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2022-01-18 11:29:35 -08:00 |
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itag_banks.sv
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tag range reductions
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2020-01-21 19:07:55 -08:00 |
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l1_arbiter.sv
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l1arb cleanup
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2020-06-30 11:04:00 -07:00 |
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load_queue.sv
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seperated load and store queues
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2022-01-18 11:29:35 -08:00 |
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load_store_queue.sv
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seperated load and store queues
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2022-01-18 11:29:35 -08:00 |
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load_store_unit.sv
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CSR read separated from LS path
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2022-01-18 11:29:35 -08:00 |
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lut_ram.sv
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paramaterized read ports on basic LUTRAM block
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2020-06-03 13:50:20 -07:00 |
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mmu.sv
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added support to abort MMU requests
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2022-01-18 11:29:35 -08:00 |
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msb.sv
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final changes for verilator support
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2018-12-19 12:04:48 -08:00 |
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msb_naive.sv
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changes for vivado simulation
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2019-09-03 16:48:58 -07:00 |
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mstatus_priv_reg.sv
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changes for verilator support
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2018-11-29 13:44:33 -08:00 |
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mul_unit.sv
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bug fixes
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2020-06-16 16:48:27 -07:00 |
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one_hot_occupancy.sv
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trimmed two_plus output
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2019-08-21 13:12:25 -07:00 |
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one_hot_to_integer.sv
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execution and writeback changes for new ID system
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2020-06-03 13:50:20 -07:00 |
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placer_randomizer.sv
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helper for placement randomization
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2019-01-03 12:39:09 -08:00 |
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ras.sv
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RAS changes for early branch correction
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2022-01-18 11:29:35 -08:00 |
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reg_inuse.sv
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code cleanups
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2020-01-22 19:59:33 -08:00 |
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regfile_bank_sel.sv
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regfile fix
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2020-06-07 20:27:51 -07:00 |
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register_file.sv
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parameterized number of read ports on regfile
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2020-06-07 14:07:33 -07:00 |
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register_file_and_writeback.sv
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seperated load and store queues
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2022-01-18 11:29:35 -08:00 |
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riscv_types.sv
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system op decode changes
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2022-01-18 11:29:35 -08:00 |
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set_clr_reg_with_rst.sv
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code cleanup: converted set/clr register usage into a module
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2020-04-02 15:32:02 -07:00 |
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shift_counter.sv
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cleaning up repo
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2022-01-18 11:29:35 -08:00 |
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store_queue.sv
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seperated load and store queues
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2022-01-18 11:29:35 -08:00 |
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tag_bank.sv
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minor cleanups
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2020-06-30 11:06:07 -07:00 |
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taiga.sv
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CSR read separated from LS path
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2022-01-18 11:29:35 -08:00 |
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taiga_config.sv
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CSR read separated from LS path
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2022-01-18 11:29:35 -08:00 |
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taiga_fifo.sv
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fifo improvements
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2020-06-30 11:25:10 -07:00 |
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taiga_types.sv
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seperated load and store queues
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2022-01-18 11:29:35 -08:00 |
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tlb_lut_ram.sv
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TLB updates
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2022-01-18 11:29:35 -08:00 |
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toggle_memory.sv
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in-flight reset support
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2020-06-26 16:37:59 -07:00 |
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wishbone_master.sv
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code cleanup: converted set/clr register usage into a module
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2020-04-02 15:32:02 -07:00 |
