* pmp: Fix csr
- Add proper granularity (G=1)
- Disallow NA4
- Fix read of pmpaddr
- Add PMP benchmark to CI
Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
* Fix mcounteren/scounteren CSR logic
The privilege check should verify that the __current__ privilege level has
access to the counter CSRs. Before it checked if the privilege level of
the CSR instruction has access to the counters. Essentially, the m-mode
could not access any counter csr if mcounteren/scounteren was not set.
* Fix pmpcfg csr incase of NA4
The next pmpcfg register value needs to be set to the previous value if
NA4 is selected.
The tests have been spread to many smaller tests previously to avoid CI timeouts.
With memory preloading the overhead of setting up the tests is dominating so we
merge the tests again.
Also remove `rv64ui-v-fence_i` from test list as it is currently failing.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
Pre-load the Verilator memories through a side-band signal. We have sub-classed
the dtm_t module to prevent the debugger from pre-loading. This commit also
updates the stale bootrom.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
The riscv-fesvr repo has been merged with Spike. This commit removes
the legacy install and updates riscv-isa-sim to the latest version.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
The CI timed out many times due to overly long GCC builds (and checkouts).
This commit rectifies this issue and downloads pre-built toolchains and
Verilator builds.
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
* Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals.
* saving...
* ⬆️ Updates for new FPU
* Add sv fpu to FPGA flow
* Use multi-threading capabilities of verilator
- Deactivate non-standard floating point arguments
- Make multi-threading conditional on the availability of verilator 4
* Remove DPI threadsafety
* Reduce FPGA clock frequency
- Remove couple of -v- tests to reduce test-time
* Fix documentation and fpga flow
- Fix cycle time to accommodate FPU
- Fix FPGA constraints
* Change UART frequency
* Fix latch and timing loop in debu_req
* Fix unconnected IPI signals in CLINT, and unconnected regs in CSR_REGFILE
* Fix several issues with AXI IDs in axi_adapter, add AXI ID width parameter, and assertions testing for invalid read/write data
* Eliminate sim, simc make targets for Questa. Tests can be directly invoked via typing name and optionally specifying the gui-mode.
* Initialize instruction traced shadow regfile to zero at start of simulation
Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X
Fix printouts of assertions
Modify bootrom to prevent assignment of X to output
* Make separate CI target for AMO tests
* Bump fpga-support version
* Add AMO tests list
* Fix FPU submodule version
* Change core_id + cluster_id into hart_id
* Rename gitlab CI tests
* Replace all SYNTHESIS macros with pragma translate_off
* Update readme, bump common cells, benderize
* Fix torture make target
* Remove unneeded signal
