Guillaume Chauvon
66f158dea0
FPGA: Add scripts to boot linux fpga ( #924 )
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Signed-off-by: Guillaume Chauvon<guillaume.chauvon@thalesgroup.com>
2022-06-28 09:59:51 +02:00
Guillaume Chauvon
909d85a56c
Fix tc_srams paths ( #892 )
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* cva6_synth.tcl: fix set_input_delay and set_output_delay tc_sram paths
* ariane_tb.cpp;.sv: [Fix tc_srams] change path for user memory preload
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2022-05-30 22:50:50 +02:00
JeanRochCoulon
35f430d8c6
Replace SyncDpRam by tc_ram ( #861 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2022-04-28 20:13:55 +02:00
JeanRochCoulon
56f8c9f5fe
Add user field between memory and caches ( #857 )
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* wt_dcche_wbuffer.sv: fix assert
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Many files: Add user between memories and cva6
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Update std_nbdcache.sv
Make wb cache work
* Update setup.sh
Co-authored-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2022-04-20 12:47:07 +02:00
Luca Colagrande
75250868eb
wb_dcache: Forward atomic transactions to AXI ( #777 )
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* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
2022-03-09 16:33:37 +01:00
Nils Wistoff
fc817af76c
tb_wt_dcache: Add AXI include dir
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-11 10:50:36 +01:00
Nils Wistoff
52c343c106
tb_cva6_icache: Add cf_math_pkg dependency
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-11 10:50:36 +01:00
Nils Wistoff
c419da3457
tb_wb_dcache: Provide ArianeCfg as cache parameter
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-11 10:50:36 +01:00
Nils Wistoff
22b67049f7
tb_wb_dcache: Add AXI includedir
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-11 10:50:36 +01:00
Andreas Kuster
c72a9e5d56
Bump register interface to v0.3.1 ( #819 )
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* Bump register interface to v0.3.1
* Upgrade PLIC to upgraded register interface version v0.3.1
* Upgrade rv_plic submodule
* Add rv_plic upgrade to xilinx target. Fix indentations
* Try again (indentation)
* Add register_interface include
2022-02-10 14:19:12 +01:00
Nils Wistoff
741e82133d
ariane_testharness/ariane_xilinx: Fix AXI ID width ( #813 )
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- Fix the AXI ID width for the CLINT (previously `4`, now `5`)
- Parametrise the CLINT's AXI types
- Deprecate `axi_[master|slave]_connect` and move to AXI assign macros,
as they allow arbitrary AXI types
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-02-06 11:17:21 +01:00
Noah Huetter
da74358206
Remove debug module from devicetree ( #806 )
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* remove debug module from devicetree
* replace uart compatible string with one that uses the FiFos
* regenerate bootrom
* regenerate FPGA bootrom
Signed-off-by: Noah Huetter <huettern@iis.ee.ethz.ch>
Co-authored-by: Noah Huetter <huettern@iis.ee.ethz.ch>
2022-01-31 15:37:48 +01:00
Nils Wistoff
497236818f
ariane_xilinx: Fix xbar clock ( #799 )
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Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2022-01-22 08:47:26 +01:00
Michael Rogenmoser
4bdfa69d20
axi and common_cells upgrade (#791 )
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* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
2022-01-15 11:08:14 +01:00
Gchauvon
360c34af69
cvxif: Flist modifications for core-v-verif and synthesis ( #781 )
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Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2021-12-29 14:58:54 +01:00
Gchauvon
e197b445fc
Add cv-x-interface ( #780 )
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* Add top hierarchy modification and rs3 for general purpose register file
* CVA6 core modifications to enable CoreV-eXtension-Interface feature
* Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6
* CoreV-eXtension-Interface available for FPGA
* Add work directories to gitignore
* Flist: fix cvxif files
* CVXIF: Modification and bugfix for cvxif feature
* CVXIF: simplify destination register feature
* Make 3rd read port on regfile configurable
* example_copro: use fifo_v3 instead of stream_fifo
* Makefile: compilation copro using defines
* ariane_pkg,riscv_pkg: add parameter to en/disable cvxif
* cva6.sv, ariane.sv: add hierarchy between ariane and cva6
* Clean Up code and typo
* CVXIF: moved combinatorial part to cvxif_fu module in ex_stage
* instr_decoder: rename instr predecoder and package
* Clean Up code and typo
* cvxif modification to follow style guideline
* issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
2021-12-22 12:31:56 +01:00
Luca Colagrande
bb9821d85f
tb_*cache: Update source list ( #776 )
2021-12-07 15:23:37 +01:00
pawelkudlakaldec
43b3608fe8
Explicit void type should be used for read_section function ( #771 )
2021-11-30 13:51:11 +01:00
Gchauvon
e7dd85d4f9
elfloader.cc: change read_section prototype ( #767 )
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as read_section does not return any value, return type is void.
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2021-11-23 09:13:55 +01:00
André Sintzoff
5c5c704d1d
debug_disable and time_out via $plusargs (#757 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2021-10-18 17:41:11 +02:00
André Sintzoff
fd8e971f1e
Clean-up flists ( #750 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2021-10-09 10:17:39 +02:00
André Sintzoff
a551e59f47
ariane_tb.cpp: fix memory loading size ( #749 )
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Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2021-10-05 19:43:40 +02:00
André Sintzoff
43677af151
riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug ( #746 )
2021-10-01 17:02:34 +02:00
Nils Wistoff
a896d0cf57
ariane_testharness: Fix ariane port list ( #742 )
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Update the portlist of ariane's instantiation according to its
definition (ariane.sv:45,49)
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2021-10-01 11:31:37 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
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* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
