The second optimization for Altera FPGA is to move the BHT to LUTRAM. Same as before, the reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the BHT.
The main changes to the existing code are:
New RAM module to infer synchronous RAM in altera with 2 independent read ports and one write port (SyncThreePortRam.sv)
Changes in the frontend.sv file: modify input to vpc_i port of BHT, by advancing the address to read, in order to compensate for the delay of synchronous RAM.
Changes in the bht.sv file: This case is more complex because of the logic operations that need to be performed inside the BHT. First, the pc pointed by bht_update_i is read from the memory, modified according to the saturation counter and valid bit, and finally written again in the memory. The prediction output is given based on the vpc_i. With asynchronous memory, the new data written via update_i is available one clock cycle after writing it. So, if vpc_i tries to read the address that was previously written by update_i, everything is fine. However, in the case of synchronous memory there are three clock cycles of latency (one for reading the pc content (read port 1), another one for writing it, and another one for reading in the other port (read port 0)). For this reason, there is the need to adapt the design to these new latency constraints:
First, there is the need for a delay on the address write of the synchronous RAM, to wait for the previous pc read and store the right modified data.
Once this is solved, similarly to the FIFO case, there is the need for an auxiliary buffer that will store the data written in the FIFO, allowing to have it available 2 clock cycles after the update_i was valid. This is because after having the correct data, the RAM takes 2 clock cycles until data can be available in the output (one clock cycle for writing and one for reading).
Finally, there is a multiplexer in the output that permits to deliver the correct prediction providing the data from the update logic (1 cycle of delay), the auxiliary register (2 cycles of delay), or the RAM (3 or more cycles of delay), depending on the delay since the update_i was valid (i.e. written to the memory).
The first optimization for Altera FPGA is to move the instruction queue to LUTRAM. The reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the instruction queue and FIFOs inside wt axi adapter.
The main changes to the existing code are:
New RAM module to infer synchronous RAM in altera with independent read and write ports (SyncDpRam_ind_r_w.sv)
Changes inside cva6_fifo_v3 to adapt to the use of synchronous RAM instead of asynchronous:
When the FIFO is not empty, next data is always read and available at the output hiding the reading latency introduced by synchronous RAM (similar to fall-through approach). This is a simplification that is possible because in a FIFO we always know what is the next address to be read.
When data is read right after write, we can’t use the previous method because there is a latency to first write the data in the FIFO, and then to read it. For this reason, in the new design there is an auxiliary register used to hide this latency. This is used only if the FIFO is empty, so we detect when the word written is first word, and keep it in this register. If the next cycle comes a read, the data out is taken from the aux register. Afterwards the data is already available in the RAM and can be read continuously as in the first case.
All this is only used inf FpgaAlteraEn parameter is enabled, otherwise the previous implementation with asynchronous RAM applies (when FpgaEn is set), or the register based implementation (when FpgaEn is not set).
* A new type of exception, custom_exception, was created.
This exception is raised when the cause is unknow, it
will end the test.
It will write 0 in mtval
Signed-off-by: Jules Fauchon <jules.fauchon@thalesgroup.com>
* Spike was deconding CUS_ADD even if func7 was not equal to 0.
A test was added so now it will raise an illegal instruction.
Signed-off-by: Jules Fauchon <jules.fauchon@thalesgroup.com>
to have same behaviour on spike and on RTL with one core,
do not yield load reservation at the end of each block of
INTERLEAVE steps
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Updates bit templateswith the new spec.
* Adds enums to cvxif.h for switch/case in cvxif.cc when instructions are decoded.
* Adds the number of source registers accepted (2 or 3) as a parameter to the `processor_t` class (processor.h).
* Adds an option in spike.cc to specify the number of source registers.
Signed-off-by: Jules FAUCHON <jules.fauchon@thalesgroup.com>
* vendor/riscv/riscv-isa-sim/customext/cvxif.cc (toplevel): Include new
header.
(cvxif_t::do_writeback_p): Replace deprecated (?) MATCH_CUSTOM3 with the
corresponding numerical value.
(cvxif_t::custom_3): Use templated load and store methods.
* vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc (toplevel): Include new
header.
NOTE: patch preparation process needs improvement.
vendor.py message:
INFO: Cloned at revision fcbdbe7946079650d0e656fa3d353e3f652d471f
INFO: Copying upstream sources to vendor/riscv/riscv-isa-sim
INFO: Applying patch vendor/patches/riscv/riscv-isa-sim/0001-generate-shared-fesvr-lib.patch at vendor/riscv/riscv-isa-sim
Checking patch vendor/riscv/riscv-isa-sim/fesvr/fesvr.mk.in...
Hunk #1 succeeded at 18 (offset -2 lines).
Applied patch vendor/riscv/riscv-isa-sim/fesvr/fesvr.mk.in cleanly.
INFO: Applying patch vendor/patches/riscv/riscv-isa-sim/0002-improve-extension-loading-diagnostics.patch at vendor/riscv/riscv-isa-sim
Checking patch vendor/riscv/riscv-isa-sim/riscv/extensions.cc...
Applied patch vendor/riscv/riscv-isa-sim/riscv/extensions.cc cleanly.
INFO: Applying patch vendor/patches/riscv/riscv-isa-sim/0003-add-cvxif-extension.patch at vendor/riscv/riscv-isa-sim
Checking patch vendor/riscv/riscv-isa-sim/customext/customext.mk.in...
Checking patch vendor/riscv/riscv-isa-sim/customext/cvxif.cc...
Checking patch vendor/riscv/riscv-isa-sim/customext/cvxif_test.c...
Checking patch vendor/riscv/riscv-isa-sim/riscv/cvxif.h...
Checking patch vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc...
Checking patch vendor/riscv/riscv-isa-sim/riscv/riscv.mk.in...
Hunk #1 succeeded at 20 (offset -6 lines).
Applied patch vendor/riscv/riscv-isa-sim/customext/customext.mk.in cleanly.
Applied patch vendor/riscv/riscv-isa-sim/customext/cvxif.cc cleanly.
Applied patch vendor/riscv/riscv-isa-sim/customext/cvxif_test.c cleanly.
Applied patch vendor/riscv/riscv-isa-sim/riscv/cvxif.h cleanly.
Applied patch vendor/riscv/riscv-isa-sim/riscv/cvxif_base.cc cleanly.
Applied patch vendor/riscv/riscv-isa-sim/riscv/riscv.mk.in cleanly.
INFO: Changes since the last import:
* triggers: native triggers (action=0) should prevent causing a
breakpoint exception while already in a trap handler (YenHaoChen)
* Add clear in_wfi interface to proc_t (Jerry Zhao)
* Close file descriptors in destructor of syscall_t (Yinan Xu)
* Partially revert riscv/riscv-isa-sim#1326 (Andrew Waterman)
* Avoid declaring potentially out-of-bounds references in vmfeq etc.
(Andrew Waterman)
* Rename parameters for VI_VFP_NCVT* macros to be consistent with the
comments in vfncvt*.h (Weiwei Li)
* Fix comments error in vfncvt_*_w.h (Weiwei Li)
* Remove unused parameter for macro in v_ext_macro.h (Weiwei Li)
* Make some dtm_t interfaces protected (Jerry Zhao)
* Unify fesvr/debug_defines.h and riscv/debug_defines.h (Jerry Zhao)
* Add debug_defines.h to list of installed headers (Jerry Zhao)
* explicitly show D(-mode) instead of M(-mode) when in debug mode
(YenHaoChen)
* Implement pending bits for plic (Jiajie Chen)
* Decrement icount trigger count on external interrupt (Scott Johnson)
* Don't waste time checking icount when unnecessary (Scott Johnson)
* Initialize all fields of icount_t (Scott Johnson)
* Allow client to override default names of caches (Jakub Palider)
* Print cache stats even when no access (Jakub Palider)
* Add cache statistics print on demand (Jakub Palider)
* Implement Zfa. (Philipp Tomsich)
* encoding.h: regenerate (Philipp Tomsich)
* gitignore: ignore emacs backup files (Philipp Tomsich)
* Fix --bootargs default value in spike usage help() function (Julien
Olivain)
* Stop unconditionally adding zicntr_zihpm to extensions (Jerry Zhao)
* Support zihpm && !zicntr (Jerry Zhao)
* Set counteren_mask properly when !(zihpm && zicntr) (Jerry Zhao)
* Add zicntr_zihpm to DEFAULT_ISA (Jerry Zhao)
* Update configure/config.h.in (Jerry Zhao)
* Add processor_t::is_waiting_for_interrupt accessor (Jerry Zhao)
* interactive: Improve ctrlc responsiveness (Jerry Zhao)
* Fix for https://github.com/riscv-software-src/riscv-isa-
sim/issues/1291 (Tommy Murphy)
* Implement Smrnmi extension (Andrew Waterman)
* Make MPRV logic consistent; factor it out (Andrew Waterman)
* Update encoding.h for Smrnmi CSR and opcode definitions (Andrew
Waterman)
* Fix the relationship between Zce and Zcf (Weiwei Li)
* fesvr: fix compilation with gcc 13 (Julien Olivain)
* Use simif_t instead of sim_t for clint/plic (Scott Johnson)
* Switch debug_module to use simif_t instead of sim_t (Scott Johnson)
* Move debug_mmu used by debug_module up to simif_t (Scott Johnson)
* Move methods used by debug_module/clint/plic up to simif_t (Scott
Johnson)
* Add virtual/override to sim_t declarations (Scott Johnson)
* fesvr: Add --symbol-elf flag to populate htif-t::symbol_elfs (Jerry
Zhao)
* fesvr: Add symbol_elfs field to htif_t (Jerry Zhao)
* Fix ctrl-c responsiveness when running-silent in interactive mode
(Jerry Zhao)
* fesvr: Fix brace style in htif_t::load_program (Jerry Zhao)
* fesvr: fix +signature-granularity opt parsing to be required_arg
(Jerry Zhao)
* fesvr: Add +target-argument= flag to htif parsing (Jerry Zhao)
* fesvr: Fix spacing in parse_arguments (Jerry Zhao)
* fesvr: target_args() should return a const (Jerry Zhao)
* make target_args() protected instead of private to allow subclasses
to inject args (Sagar Karandikar)
* Don't issue misaligned or non-power-of-2 MMIO accesses (Scott
Johnson)
* Fix misaligned accesses to clint's msip regs (Scott Johnson)
* Improve plic_context_t initialization style (Andrew Waterman)
* Initialize MTIP at reset (Scott Johnson)
* Define sim_t::INTERLEAVE so that it can be accessed by reference
(Andrew Waterman)
* Support discontiguous hart IDs in CLINT (Andrew Waterman)
* Fix PLIC on big-endian hosts (Andrew Waterman)
* Remove unnecessary conditional in plic_t::load (Andrew Waterman)
* Correctly instantiate PLIC contexts for mixed-hart targets (Andrew
Waterman)
* Refactor plic_t and plic_context_t initialization (Andrew Waterman)
* Remove unused plic_context_t::num field (Andrew Waterman)
* Remove unused plic_t::procs field (Andrew Waterman)
* Make debug module tolerant of discontiguous hart IDs (Andrew
Waterman)
* Add cfg_t::max_hartid accessor (Andrew Waterman)
* Add sim_t::get_harts and sim_t::get_cfg accessors (Andrew Waterman)
* Improve input validation for --hartids flag (Andrew Waterman)
* Use size_t, rather than int, for hartids (Andrew Waterman)
* Return periodically from interactive_run and interactive_until
(Andrew Waterman)
* Add ability to partially complete and resume interactive routines
(Andrew Waterman)
* Return from sim_t::interactive() when there's no more input (Andrew
Waterman)
* fesvr: elfloader: replace asserts after open and mmap by exceptions
(Viktor Prutyanov)
* optimize `num_ids_word` init logic; init `max_prio` by
initialization-list (Wade)
* Remove redundant RVE related check in cm.mva01s and cm.mvsa01
(Weiwei Li)
* Add r1s != r2s check for cm.mvsa01 (Weiwei Li)
* Update fields name for sreg1/sreg2 (Weiwei Li)
* Add support for 'zce' in isa string (Weiwei Li)
* Rename host_pte_paddr to host_pte_addr (Scott Johnson)
* fix unintentionally plic context update when `val > max_prio` and
`offset == CONTEXT_THRESHOLD` (Wade)
* Disable Zvfh when Zfhmin is disabled (Weiwei Li)
* Disable Zvfh{min} when misa.V is cleared (Weiwei Li)
* Disable Zfh{min} when misa.F is cleared (Weiwei Li)
* Do not ignore tdata1 writes unless they really would set dmode=1
(Scott Johnson)
* Defer init of type/tdata2/tdata3 until needed (Scott Johnson)
* Support dynamically disabling misa.C once again (Andrew Waterman)
* Make JVT CSR definition account for dynamically disabling Zcmt
(Andrew Waterman)
* Add infrastructure to dynamically disable multi-letter extensions
(Weiwei Li)
* Avoid magic number in dts generation's default pmpgranularity (Jerry
Zhao)
* Skip all dts/dtb-related steps if !dtb_enabled (Jerry Zhao)
* Use sv57 paging for rv64 configurations (Jerry Zhao)
* Set cfg-provided processor_t.pmp_num before parsing the dtb (Jerry
Zhao)
* Don't reset sim_t if there is no dts for get_dts (Jerry Zhao)
* Pass dtb_file directly to make_dtb (Jerry Zhao)
* PKBB32, PKTT32 removed (Replaced by PACK and PACKU of Zbp
respectively) (Neel Gala)
* Use relative path for fesvr/byteorder.h in mmu.h (Jerry Zhao)
* Remove decode_macros.h from disasm.h (Jerry Zhao)
* Add disasm/extension/rocc.h to installed headers (Jerry Zhao)
* Remove dependency on decode_macros in rocc.h (Jerry Zhao)
* Fix insn_desc_t formation on push_custom_insn (Jerry Zhao)
* Make htif->get_to/fromhost_addr methods public (Jerry Zhao)
* Zicond: implement Zicond (conditional integer operations) (Philipp
Tomsich)
* Update encoding.h for Zicond opcodes (Andrew Waterman)
* triggers: optimize icount_t::icount_check_needed() (YenHaoChen)
* triggers: update README.md: add icount trigger (YenHaoChen)
* triggers: add detect_icount_match() (YenHaoChen)
* triggers: force to slow path with icount triggers (YenHaoChen)
* triggers: add icount_t and update tinfo (YenHaoChen)
* triggers: if match triggers with both breakpoint exception and
entering D-mode, then enter D-mode and ignore breakpoint exception
(YenHaoChen)
* triggers: refactor: use CSR_TDATA1_TYPE_MCONTROL6 instead of number
6 (YenHaoChen)
* Remove dirty_enabled from cfg_t (Aaron Durbin)
* Remove --mmu-dirty command line flag (Aaron Durbin)
* Use Svadu control bits to drive A/D updates (Aaron Durbin)
* Enable Svadu control bits in menvcfg and henvcfg (Aaron Durbin)
* Add Svadu CSR bit definitions (Aaron Durbin)
* Add Svadu Extension Parsing to ISA Parser (Aaron Durbin)
* Improve PMP number/granularity error messages (Andrew Waterman)
* Perform pmpregions input validation in only one place (Andrew
Waterman)
* Support all 64 PMP registers (Andrew Waterman)
* Add --triggers flag to select number of triggers (Jerry Zhao)
* Instantiate tdata/tinfo as const csrs when trigger_count == 0 (Jerry
Zhao)
* Add trigger_count field to cfg_t (Jerry Zhao)
* Add htif_t tohost/fromhost accessors (Jerry Zhao)
* Add more hint when searched path is wrong (gr816ox)
* Simplify isa_parser_t::extension_enabled (Andrew Waterman)
* Keep max_isa and extension_table in sync in exactly one place
(Andrew Waterman)
* Use more appropriate data structure for extension_table (Andrew
Waterman)
* Lift artificial limit of 191 extensions (Andrew Waterman)
* triggers: refactor: use static and remove const for
legalize_action() (YenHaoChen)
* triggers: refactor: use static and remove const for legalize_match()
(YenHaoChen)
* triggers: refactor: remove legalization_action()'s dependency on
dmode (YenHaoChen)
* triggers: legalize timing=1(after) for load data trigger
(YenHaoChen)
* triggers: refactor: remove an outdated comment (YenHaoChen)
* triggers: refactor: add mcontrol_common_t::legalize_timing()
function (YenHaoChen)
* Run Spike and HTIF in a single thread, rather than two (Andrew
Waterman)
* For NS16550 UART, poll stdin less often (Andrew Waterman)
* Automatically test that external debug still works. (Tim Newsome)
* Use nproc or hw.ncpu instead of -j4 to build spike. (Tim Newsome)
* Refactor build-spike out of test-spike. (Tim Newsome)
* Fix supported debug version, use extension names (Tim Newsome)
* improve merge_mem_regions to handle memory region covering the whole
64-bit address space (Parshintsev Anatoly)
* change mem_cfg_t to accept cases when (base + size) is at 64-bit
address space border (Parshintsev Anatoly)
* simplify check_mem_overlap by utilizing get_inclusive_end of
mem_cfg_t (Parshintsev Anatoly)
* simplify merge_mem_regions by utilizing get_inclusive_end() of
mem_cfg_t (Parshintsev Anatoly)
* get_inclusive_end implementation for mem_cfg_t (Parshintsev Anatoly)
* implement get_size() getter for mem_cfg_t object (Parshintsev
Anatoly)
* implement get_base() getter for mem_cfg_t object (Parshintsev
Anatoly)
* Remove vestigial UNUSED annotation (Andrew Waterman)
* Only update histogram when histogramming (Andrew Waterman)
* Remove --enable-dirty compile option (Jerry Zhao)
* Respect --mmu-dirty flag instead of --enable-dirty (Jerry Zhao)
* Add --mmu-dirty runtime flag (Jerry Zhao)
* Add cfg_t field to enable PTE dirtying (Jerry Zhao)
* Untabify ci-tests/testlib.c (Jerry Zhao)
* Fix debug-mode regression introduced by 20e7f53 (Jerry Zhao)
* triggers: refactor: move mode_match() and textra_match() to private
for protected (YenHaoChen)
* triggers: refactor: create trigger_t::common_match() (YenHaoChen)
* triggers: refactor: move textra_match() to protected from public
(YenHaoChen)
* triggers: refactor: move textra_match() into
detect_trap_match::detect_trap_match() (YenHaoChen)
* triggers: refactor: move textra_match() into
mcontrol_common_t::detect_memory_access_match() (YenHaoChen)
* triggers: refactor: move detect_trap_match() to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: create virtual function
trap_common_t::simple_match() (YenHaoChen)
* triggers: refactor: move get_action() to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: move get_dmode() to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: move action variable to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: move hit variable to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: move dmode variable to trap_common_t from
itrigger_t/etrigger_t (YenHaoChen)
* triggers: refactor: add empty parent trap_common_t class for
itrigger_t and etrigger_t (YenHaoChen)
* Delete --enable-misaligned configure option (Andrew Waterman)
* Respect --[no-]misaligned command-line flag (Andrew Waterman)
* Add --[no-]misaligned command-line options (Andrew Waterman)
* Pass cfg object to processor_t constructor (Andrew Waterman)
* triggers: refactor: add bool etrigger_t::simple_match() (YenHaoChen)
* triggers: refactor: add bool itrigger_t::simple_match() (YenHaoChen)
* Make misa.C read-only (Andrew Waterman)
* Support pte load/store from mmio regions (Jerry Zhao)
* Pull pte load/store into methods of mmu_t (Jerry Zhao)
* Add method to probe which memory regions are reservable (Jerry Zhao)
* Remove extraneous semicolon from simif.h (Jerry Zhao)
* Specify addresses are physical for simif_t member functions (Jerry
Zhao)
* Make obvious that PC alignment mask is a function of IALIGN (Andrew
Waterman)
* Prevent processor_t from retiring instructions after a WFI (Jerry
Zhao)
* Change address used in gdb debug example. (Tim Newsome)
* Add mmio_fetch to simif_t to distinguish between fetch/load for mmio
accesses (Jerry Zhao)
* Remove dead code in Makefile.in (Andrew Waterman)
* Remove non-installed header lists from Makefile fragments (Andrew
Waterman)
* Fix build nondeterminism by deleting archives before recreating
(Andrew Waterman)
* Speed up histogramming by changing data structure (Andrew Waterman)
* Sort histogram printout count, rather than address (Andrew Waterman)
* Remove --enable-histogram option (Andrew Waterman)
* Only clear logging structures if logging is enabled (Andrew
Waterman)
* Always use slow path for histogramming (Andrew Waterman)
* Support histogram regardless of configure flag (Andrew Waterman)
* Reduce compile time increase introduced by riscv/riscv-isa-sim#1189
(Andrew Waterman)
* triggers: add mcontrol6 trigger (YenHaoChen)
* triggers: refactor: add mcontrol_common_t::legalize_match() function
(YenHaoChen)
* triggers: refactor: remove redundant namespace qualifiers
(YenHaoChen)
* triggers: refactor: extract mcontrol_common_t from mcontrol_t
(YenHaoChen)
* triggers: refactor: update trigger_t::mode_match() (YenHaoChen)
* triggers: refactor: add trigger_t::mode_match() function
(YenHaoChen)
* Support more than 65 Z* extensions (Andrew Waterman)
* triggers: refactor: move m/s/u/vs/vu to trigger_t (YenHaoChen)
* triggers: refactor: add mcontrol.vs and mcontrol.vu (YenHaoChen)
* triggers: refactor: cleaner vs and vu checking (YenHaoChen)
* Always build with commit logging support (Jerry Zhao)
* Add logged instruction variants to insn_desc_t (Jerry Zhao)
* Add logged variants of insn templates (Jerry Zhao)
* Replace compile-time commitlog check with runtime check for vector
writes (Jerry Zhao)
* Replace compile-time conditional with run-time conditional for
load/store logging (Jerry Zhao)
* Split execute_insn into fast and logged variants (Jerry Zhao)
* Force slow-path when commit-logging is enabled (Jerry Zhao)
* Always compile commit-log utility functions (Jerry Zhao)
* Check commitlog-enable dynamicallly for csr_t::log_special_write
(Jerry Zhao)
* Always reset commit logging variables (Jerry Zhao)
* Always perform symbol lookup in debug (Jerry Zhao)
* Fix compile error in commit-logging code (Jerry Zhao)
* Allow reads/writes to reserved CLINT regions (Jerry Zhao)
* arith.h: remove redundant y1 = t; in mulhu(uint64_t, uint64_t)
(Serdar Sayın)
* Add github actions test that installed headers are usable (Jerry
Zhao)
* Remove processor.h/sim.h -> config.h dependencies (Jerry Zhao)
* Add missing vector_unit.h to install headers list (Jerry Zhao)
* Remove entropy_source.h -> internals.h dependency (Jerry Zhao)
* Add missing abstract_interrupt_controller.h to header lists (Jerry
Zhao)
* Remove debug_module.h -> mmu.h dependency (Jerry Zhao)
* Use relative include paths to support public usage of these headers
(Jerry Zhao)
* Don't install instruction decode macros (Jerry Zhao)
* Add config.h includes directly to source files instead of relying on
header chaining (Jerry Zhao)
* Add github actions test on macos (Jerry Zhao)
* Fix build broken by riscv/riscv-isa-sim#1170 and riscv/riscv-isa-
sim#1180 (Andrew Waterman)
* Print better error message when requesting >1024 harts (Andrew
Waterman)
* Rename memif_endianness_t to endianness_t (Jerry Zhao)
* Pull memif_endianness_t into cfg.h (Jerry Zhao)
* Add cfg.cc to hold internal implementation of mem_cfg_t (Jerry Zhao)
* Split decode.h into public decode.h and private decode_macros.h
(Jerry Zhao)
* Fix build on M1 (Andrew Waterman)
* Move boost asio socket interface to socketif_t (Jerry Zhao)
* Make the processor_t interface independent of configure'd variables
(riscv/riscv-isa-sim#1174) (Jerry Zhao)
* Pull vector unit into separate source/header (Jerry Zhao)
* Pull p/v_ext_macros.h out of decode.h (Jerry Zhao)
* Add Emacs lockfiles to .gitignore (riscv/riscv-isa-sim#1171) (Jerry
Zhao)
* Move mhselect_compare into mhselect_interpretation (Scott Johnson)
* Use interpret_mhselect() to decide textra compare mode (Scott
Johnson)
* Interpret mhselect in centralized place (Scott Johnson)
* triggers: add mcontext and hcontext CSRs (YenHaoChen)
* triggers: add scontext CSR (YenHaoChen)
* triggers: checking textra (tdata3); checking ASID and VMID
(YenHaoChen)
* triggers: implement tdata3 CSR fields (YenHaoChen)
* refactor: add tdata3_csr_t; preparation for CSR textra (YenHaoChen)
* refactor: remove proc parameter from functions of module_t
(YenHaoChen)
* Avoid use of sprintf in disassembler (Andrew Waterman)
* Avoid use of sprintf in trap_t (Andrew Waterman)
* SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes (Andrew
Waterman)
* Simplify implementation of SFENCE.W.INVAL (Andrew Waterman)
* clear mevent.VUINH and mevent.VSINH when misa.H is cleared
(YenHaoChen)
* add macro N_HPMCOUNTERS (29) (YenHaoChen)
* use extension_enabled('H') instead of extension_enabled_const('H')
since misa.H is RW (YenHaoChen)
* refactor: add custom CSR class, mevent_csr_t (YenHaoChen)
* Make require_novirt macro an expression, not a statement (Andrew
Waterman)
* For trap_t::name, return an std::string instead of a C string
(Andrew Waterman)
* Remove unused constructor arg from match_result_t (Scott Johnson)
* Remove no-longer-used match_result_t.fire (Scott Johnson)
* Use std::optional for detect_trap_match in trigger_t hierarchy
(Scott Johnson)
* Convert triggers::module_t::detect_trap_match to std::optional
(Scott Johnson)
* Remove unnecessary logical-or (Scott Johnson)
* Use std::optional for detect_memory_access_match in trigger_t
hierarchy (Scott Johnson)
* Convert triggers::module_t::detect_memory_access_match to
std::optional (Scott Johnson)
* Extract common method for legalizing trigger action field (Scott
Johnson)
* Add noexcept to trigger-matching functions (Scott Johnson)
* Remove no-longer-useful trigger_with_tdata2_t (Scott Johnson)
* Move tdata2 into parent class (Scott Johnson)
* triggers: s and u of mcontrol dependents on extension support
(YenHaoChen)
* triggers: legalize mcontrol.action (YenHaoChen)
* triggers: add debug log of trigger action (YenHaoChen)
* triggers: refactor: rename memory_access_match() to
detect_memory_access_match() (YenHaoChen)
* triggers: add etrigger_t (YenHaoChen)
* triggers: add itrigger_t (YenHaoChen)
* triggers: refactor: add action_t::ACTION_MAXVAL (YenHaoChen)
* refactor: let trap_t::cause() be const function (YenHaoChen)
* triggers: refactor: add take_trigger_action() to
processor.h/processor.cc (YenHaoChen)
* triggers: hardware should ignore writes that set dmode to 1 if the
previous trigger has both dmode of 0 and chain of 1 (YenHaoChen)
* triggers: hardware must zero chain in writes that set dmode to 0 if
the next trigger has dmode of 1 (YenHaoChen)
* Reimplement memory merging routines (Parshintsev Anatoly)
* triggers: refactor: remove obsolete checking of debug_mode in
disabled_trigger_t::tdata1_write() (YenHaoChen)
* triggers: refactor: use CSR_MCONTROL_DMODE(xlen) instead of
MCONTROL_DMODE(xlen) (YenHaoChen)
* triggers: dmode only writable from debug mode (YenHaoChen)
* triggers: refactor: use modern C++ loop (YenHaoChen)
* triggers: refactor: reorder functions in module_t for consistency
(YenHaoChen)
* triggers: make disabled_trigger_t as default trigger (YenHaoChen)
* triggers: refactor: use CSR_TDATA1_TYPE_MCONTROL instead of
MCONTROL_TYPE_MATCH for consistency (YenHaoChen)
* triggers: refactor: add assertions for mcontrol.type checking
(YenHaoChen)
* triggers: add disabled_trigger_t (YenHaoChen)
* triggers: mcontrol does not support VS and VU modes (YenHaoChen)
* triggers: refactor: remove return value of
mcontrol_t::tdata1_write(...) and
trigger_with_tdata2_t::tdata2_write(...) (YenHaoChen)
* triggers: refactor: move dmode checking of tdata2 to module_t for
consistency (YenHaoChen)
* triggers: refactor: let action be part of match_result_t
(YenHaoChen)
* triggers: refactor: let match_result_t be a struct with fire and
timing variables (YenHaoChen)
* update debug_defines.h (YenHaoChen)
* trigger_t: Protect destructor and memory_access_match() (Tim
Newsome)
* triggers: Move trigger_t.hit to mcontrol_t.hit (Tim Newsome)
* triggers: Access action bit through get_action() (Tim Newsome)
* triggers: rename chain (Tim Newsome)
* triggers: refactor: move dmode checking of tdata1 to module_t
(YenHaoChen)
* triggers: Rename/move dmode (Tim Newsome)
* triggers: rename store (Tim Newsome)
* Triggers: rename load (Tim Newsome)
* Restore fetch_jump_table to instruction fetch (Weiwei Li)
* Fix field extract for jvt.base (Weiwei Li)
* Fix type error in some platform (Weiwei Li)
* Enable Zcb by default in disassembler (Andrew Waterman)
* Make reserved PLIC behavior more realistic (Andrew Waterman)
* Triggers rename execute (Tim Newsome)
* Move tdata2 from mcontrol_t into its own class. (YenHaoChen)
* Add tinfo register. (Tim Newsome)
* v_ext_macros: Drop index from `VI_ELEMENT_SKIP` (riscv/riscv-isa-
sim#1151) (Dylan Reid)
* When resuming from debug mode, clear mstatus.MPRV if the new
privilege mode is less than M-mode (riscv/riscv-isa-sim#1149)
(YenHaoChen)
* Improve Zfinx error message (Andrew Waterman)
* add Zc* to README.md (Weiwei Li)
* add support for Zc* disasm (Weiwei Li)
* add support for zcmt (Weiwei Li)
* add support for zcmp (Weiwei Li)
* add support for zcb (Weiwei Li)
* add support for zca zcd and zcf (Weiwei Li)
* update encoding.h (Weiwei Li)
* add support for flags for Zc* extensions (Weiwei Li)
* Document implemented trigger configuration (riscv/riscv-isa-
sim#1145) (Scott Johnson)
* Only allow memory regions that are less than (1ull <<
MAX_PADDR_BITS) (Parshintsev Anatoly)
* get rid of redundant casts during mem layout processing (Parshintsev
Anatoly)
* Add address-cells to PLIC DTS entry (Andrew Waterman)
* fix mevent_mask for Sscofpmf extension (YenHaoChen)
* Change remaining vector FP16 instructions to require Zvfh (Andrew
Waterman)
* Change SEW=16 vfncvt.f.f.w and vfwcvt.f.f.v to require Zvfhmin
(Andrew Waterman)
* Teach ISA parser about Zvfh[min] (Andrew Waterman)
* Remove set_target_endianness | add --big-endian flag (Jerry Zhao)
* Remove memif_endianness_undecided, change default to little-endian
(Jerry Zhao)
* fix print message of size-1 accesses (YenHaoChen)
* Use reg_t, not uint64_t, for address-like quantities (Andrew
Waterman)
* Fix tval reporting for CBOs (Andrew Waterman)
* Set 16..4096-byte bound on cache-block size (Andrew Waterman)
* move fucntion cto() from processor.h to arith.h (YenHaoChen)
* Template-ize stores (Andrew Waterman)
* Template-ize loads (Andrew Waterman)
* Template-ize AMOs (Andrew Waterman)
* DRY in store-conditional instructions (Andrew Waterman)
* Simplify check_load_reservation (Andrew Waterman)
* Template-ize hypervisor loads and stores (Andrew Waterman)
* Remove require_alignment flag from loads (Andrew Waterman)
* Fix imprecise exception on LR to MMIO space (Andrew Waterman)
* Template-ize load_func macro (Andrew Waterman)
* Template-ize store_func macro (Andrew Waterman)
* No need to require_alignment for the load part of the AMO (Andrew
Waterman)
* Remove actually_store and require_alignment parameters from
store_func macro (Andrew Waterman)
* remove duplicate CMO item in README.md (Weiwei Li)
* do memcpy only for actually_store in store_slow_path_intrapage
(Weiwei Li)
* Fix missing sentinel warning in dts.cc when using gnu++17 standard
(Weiwei Li)
* Fix forced linking when compiling headers (bluew)
* fix clang build (Andrew Waterman)
* Add command to display privilege level in interactive mode (Jerry
Zhao)
* Make PLIC/NS16550 coding style more conformant (Andrew Waterman)
* Add interactive mode commands to read clint mtime/mtimecmp (Jerry
Zhao)
* Add dump memory command to interactive mode (Jerry Zhao)
* Support command-line configuration of number of pmpregions (Jerry
Zhao)
* In triggers, use optional<data> instead of {has_data, data} (Andrew
Waterman)
* Report error if an unsupported memory configuration is detected
(Parshintsev Anatoly)
* Remove unused field matched_t::data (Andrew Waterman)
* Set tval on illegal subforms of aes64ks1i (Andrew Waterman)
* Fix disassembly of RV64 srai.u (Andrew Waterman)
* Add --dm-no-abstract-fpr option. (Tim Newsome)
* Don't use reexecution as the means to implement trigger-after
(Andrew Waterman)
* Fix endianness bug in fetch triggers (Andrew Waterman)
* DRY in checking triggers (Andrew Waterman)
* Move uncommon-case fetch functionality into fetch_slow_path (Andrew
Waterman)
* Move all uncommon-case store functionality into store_slow_path
(Andrew Waterman)
* Move all uncommon-case load functionality into load_slow_path
(Andrew Waterman)
* Remove unused variable to fix build (Andrew Waterman)
* Engage non-virtual-dtor warning in CI tests (Andrew Waterman)
* Fixed -Wnon-virtual-dtor warnings (Jerin Joy)
* Expand set of warnings we error on in CI (Andrew Waterman)
* Suppress unused-variable warnings in spike main (Andrew Waterman)
* Fix unused-variable warnings in P-extension instruction definitions
(Andrew Waterman)
* Suppress unused-variable warnings in P-extension macros (Andrew
Waterman)
* Silence unused-variable warnings in auto-generated code (Andrew
Waterman)
* Fix unused-variable warnings in softfloat (Andrew Waterman)
* Suppress or fix unused-variable warnings in vector macros (Andrew
Waterman)
* Suppress unused-variable warnings in vector instruction definitions
(Andrew Waterman)
* Suppress unused-variable warnings in AES code (Andrew Waterman)
* Suppress most unused-variable warnings (Andrew Waterman)
* Silence remaining unused-parameter warnings (Andrew Waterman)
* Suppress most unused variable warnings (Andrew Waterman)
* Fix or work around other unused-parameter warnings in ancillary
programs (Andrew Waterman)
* Suppress unused-parameter warnings in spike main (Andrew Waterman)
* Add UNUSED macro for suppressing unused-parameter/variable warnings
(Andrew Waterman)
* Suppress unused-paramter warnings in softfloat (Andrew Waterman)
* Delete unused parameter in rfb_t::fb_update (Andrew Waterman)
* Suppress several unused-parameter warnings in fesvr (Andrew
Waterman)
* Fix unused-function warning on sometimes-used function cto (Andrew
Waterman)
* Delete functions that are actually unused (Andrew Waterman)
* Fix remaining ignored-qualifiers warning (Andrew Waterman)
* Fix ignored-qualifiers warnings in get_field/set_field macros
(Andrew Waterman)
* Rewrite READ_REG macro to avoid GNU statement expression extension
(Andrew Waterman)
* Rewrite require macro so it can be used as an expression (Andrew
Waterman)
* Fix trigger mcontrol.chain match issue riscv/riscv-isa-sim#599riscv/riscv-isa-sim#627 (riscv/riscv-isa-sim#1083) (YenHaoChen)
* Fix newly introduced Clang warnings (Andrew Waterman)
* Check trigger only with actually_store (YenHaoChen)
* Fix priority of mcontrol trigger store address/data before
(YenHaoChen)
* Fix priority of mcontrol trigger load address before (YenHaoChen)
* Fix priority of mcontrol trigger execute address before (YenHaoChen)
* Add has_data argument to trigger checking functions (YenHaoChen)
* Fix build using Xcode 14 (Andrew Waterman)
* Fix vmv.x.s for RV32 (Andrew Waterman)
* Update interactive.cc (XiaJin-RiVAI)
* Actually run a program in CI (Andrew Waterman)
* Build and install lib and header dependencies for Hammer (Jerin Joy)
* In CI, check that help message prints without error (Andrew
Waterman)
* Run CI with -Werror (Andrew Waterman)
* Propagate CFLAGS passed to configure into CXXFLAGS (Andrew Waterman)
* detects the loading of isa-incompatible (i.e. 32 bit code to 64bit
HART) code and emits an error message to help avoid unintentionally
loading wrong elf. (Iman Hosseini)
* Fix trigger never fire on executing an instruction on plugin devices
(riscv/riscv-isa-sim#1084) (YenHaoChen)
* Initialize triggers using default member initializers (Scott
Johnson)
* Remove obsolete enum trigger_operation_t (Scott Johnson)
* Remove redundant require_vm in macro VI_VV_LOOP_WITH_CARRY and
VI_XI_LOOP_WITH_CARRY: require_vm is also included in VI_CHECK_SSS
(Weiwei Li)
* Remove unnecessary argument alu(always false) from macro
require_vector_novtype (Weiwei Li)
* Remove redundant require_vector in macro VI_MERGE_LOOP_BASE (Weiwei
Li)
* fix comment in definition of vmv<nf>r.v (Andrew Waterman)
* vmv<nf>r.v depends on vtype, and therefore should check vill (Andrew
Waterman)
* Substantially increase context_t stack size (Andrew Waterman)
* Add disassembly support for Zbc instructions (riscv/riscv-isa-
sim#1076) (Kip Walker)
* Fix libdir and includedir in pkg-config files (riscv/riscv-isa-
sim#917) (Rupert Swarbrick)
* Fix tval on illegal instruction faults with long illegal instruction
(YenHaoChen)
* Constantize variables (Scott Johnson)
* Separate variables that contain two different things (Scott Johnson)
* Fix redundant loops when calculating vrgather.vi. (riscv/riscv-isa-
sim#1072) (yangcheng)
* "Implement" Zihintntl extension (riscv/riscv-isa-sim#1071) (Andrew
Waterman)
* Remove unused code in vsmul* (riscv/riscv-isa-sim#1069) (ksco)
* Unify PMPCFGx behaviour with PMPADDRx where PMP is disabled
(riscv/riscv-isa-sim#1068) (Greg Chadwick)
* Remove dead code in VI_VV_EXT macro (riscv/riscv-isa-sim#1065)
(ksco)
* Add space between if/while/switch and '(' (Weiwei Li)
* Improve write log for vtype in set_vl (Weiwei Li)
* Fix code indentation in processor.cc, interactive.cc,
debug_module.h/cc execute.cc, entropy_source.h and v_ext_macros.h
(Weiwei Li)
* Add missed decription for log-commits option (Weiwei Li)
* Fix description for mem related interactive commands (Weiwei Li)
* Add #ifdef RISCV_ENABLE_COMMITLOG for commitlog related code (Weiwei
Li)
* Fix exception type for accessing (v)stimecmp (riscv/riscv-isa-
sim#1061) (liweiwei90)
* update README.md (Weiwei Li)
* modify take_interrupt to support LCOFIP irq (Weiwei Li)
* add support for sscofpmf extension v0.5.2 (Weiwei Li)
* Add stateen related check for float point instructions (Weiwei Li)
* Add support for freg command to read X regs when enable Zfinx
(liweiwei)
* Modify F/D/Zfh instructions to add support for
Zfinx/Zdinx/Zhinx{min} instructions (liweiwei)
* Add flags for Zfinx/Zdinx/Zhinx{min} (liweiwei)
* Add Sstc support. (riscv/riscv-isa-sim#1057) (i2h2)
* Fix exception type for accessing senvcfg/henvcfg/hstateen (Weiwei
Li)
* add stateen related check to frm/fflags and then apply to fcsr
implicitly (Weiwei Li)
* WFI condition fix (Canberk Topal)
* DSCRATCH is now called DSCRATCH0 (Tim Newsome)
* Fix debug_rom.S build command error. (Tim Newsome)
* Fix overflow issue of p-ext multiply instructions (riscv/riscv-isa-
sim#1053) (ChunPing Chung)
* Add additional bits to medeleg (riscv/riscv-isa-sim#1050) (Brendan
Sweeney)
* Pay attention to dmcs2.grouptype. (riscv/riscv-isa-sim#1049) (Tim
Newsome)
* add base verify_permission in
counter_proxy_csr_t::verify_permissions (Weiwei Li)
* add support for time/timeh/htimedelta/htimedeltah csrs (Weiwei Li)
* modify minstret/mcycle/minstreth/mcycleh to reuse
rv32_low/high_csr_t (Weiwei Li)
* Fix load/store performance under clang (Andrew Waterman)
* Fix totally-broken misaligned HSV (Scott Johnson)
* Fix totally-broken misaligned HLV/HLVX (Scott Johnson)
* Remove no-longer-necessary typecast (Scott Johnson)
* modify the check for "state->prv >= PRV_M" to "state->prv == PRV_M"
(Weiwei Li)
* add U mode check for *envcfg* (Weiwei Li)
* Fix the initial value and write mask for mstatus (Weiwei Li)
* remove unnecessary ifdef for RISCV_ENABLE_DUAL_ENDIAN (Weiwei Li)
* extract the progress of computing the inital value of mstatus into
separate function compute_mstatus_initial_value() (Weiwei Li)
* Split up misaligned store into several steps (Scott Johnson)
* Split up misaligned load into several steps (Scott Johnson)
* add support for mconfigptr csr: it's hardwired to zero currently
(Weiwei Li)
* add support for m/henvcfgh csrs (Weiwei Li)
* Properly log mstatush side effect updates (Scott Johnson)
* Add assertion to ensure proper logging of mstatus changes on RV32
(Scott Johnson)
* Use rv32_low_csr_t for Smstateen CSRs (Scott Johnson)
* Add proxy for accessing the low 32 bits of a 64-bit CSR (Scott
Johnson)
* Remove no-longer-needed mask from rv32_high_csr_t (Scott Johnson)
* Remove unnecessary mask from rv32_high_csr_t constructor (Scott
Johnson)
* Remove mstatush mask as unnecessary (Scott Johnson)
* add check for H extension requires S mode (riscv/riscv-isa-sim#1042)
(liweiwei90)
* Add verify_permissions() for mseccfg_csr_t (YenHaoChen)
* add isa string parser for smepmp (YenHaoChen)
* Allow writes to pmp(i-1)cfg on locked pmp(i)cfg (riscv/riscv-isa-
sim#1039) (YenHaoChen)
* update README.md (Weiwei Li)
* add smstateen check for fcsr, senvcfg, henvcfg (Weiwei Li)
* add standalone class for fcsr and senvcfg csr (Weiwei Li)
* add support for csrs of smstateen extensions (Weiwei Li)
* modify mstatush_csr_t to general rv32_high_csr_t (Weiwei Li)
* add isa string parser for smstateen (Weiwei Li)
* update encoding.h (Weiwei Li)
* remove multi blank lines (Weiwei Li)
* Don't mask instruction bits (Andrew Waterman)
* Zero-extend instructions in spike-dasm (Andrew Waterman)
* Zero-extend instructions when fetching them from memory (Andrew
Waterman)
* insn_t: don't rely on sign-extension of internal encoding (Andrew
Waterman)
* update disasm for cbo.* instructions (riscv/riscv-isa-sim#1026)
(liweiwei90)
* Remove nonstandard length encoding (riscv/riscv-isa-sim#1023)
(Andrew Waterman)
* Remove the now-unused PC_SERIALIZE_WFI (Kip Walker)
* Fix RV32 hgatp write mask computation (riscv/riscv-isa-sim#1014)
(Andrew Waterman)
* Move ebreak* logic from take_trap into instructions. (riscv/riscv-
isa-sim#1006) (Tim Newsome)
* Include recently added headers in riscv/riscv.mk.in (Pirmin Vogel)
* Fix disassembly of custom instructions that overlap standard ones
(riscv/riscv-isa-sim#999) (Andrew Waterman)
* Disassemble Zicbop/Zihintpause HINT instructions (riscv/riscv-isa-
sim#1000) (Andrew Waterman)
* Update README to reflect recently added extensions (Andrew Waterman)
* Add missing Zicbom and Zicbop extensions to disassembler fallback
(Andrew Waterman)
* Add missing Q, H, and Svinval extensions to disassembler fallback
(Andrew Waterman)
* Remove now-unnecessary null check from decode_insn (Andrew Waterman)
* Assert that nullptrs can't make their way into the instructions list
(Andrew Waterman)
* Remove insn_func_t::supported field (Andrew Waterman)
* Don't register instructions that aren't supported (Andrew Waterman)
* Check for reserved PBMT values during tablewalks and fault if found
(Ryan Buchner)
* Switch from checking for SVPBMT extension to checking *ENVCFG values
during tablewalks (Ryan Buchner)
* Add PBMTE bit to menvcfg and henvcfg mask values (Ryan Buchner)
* Change henvcfg csr to a henvcfg_csr_t (Ryan Buchner)
* rvv: fix the checking eew and elen for index load (Chih-Min Chao)
* Factor out P extension macros into their own header (Andrew
Waterman)
* Factor out V extension macros into their own header (Andrew
Waterman)
* Append smepmp extension 1.0 to the feature list (soberl)
* Update pmpaddr_csr_t::access_ok() for ePMP on matching regions
(soberl@nvidia.com)
* Update mmu_t::pmp_ok() for ePMP in case matching region is not found
(soberl@nvidia.com)
* Update csr access rules for ePMP on pmpaddr and pmpcfg
(soberl@nvidia.com)
* Implement the new csr mseccfg for ePMP as dummy (soberl@nvidia.com)
* Fix the padding of register names in the log (riscv/riscv-isa-
sim#987) (Shaked Flur)
* Linking spike_dasm misses libriscv.a dependance (riscv/riscv-isa-
sim#986) (jmonesti)
* Use MCONTROL_TYPE_MATCH macro instead of 2 (Tim Newsome)
* Implement mcontrol trigger hit bit. (Tim Newsome)
* Add missing description of --dtb in --help message (Andrew Waterman)
* Add zknd zkne zknh zksed zksh disassembly support (riscv/riscv-isa-
sim#979) (Yan)
* Remove mcontrol_t.h (Tim Newsome)
* Remove maskmax as a variable. (Tim Newsome)
* Remove mcontrol_t.type. (Tim Newsome)
* Whitespace fix. (Tim Newsome)
* Pass acutally_store from store_func to misaligned_store (Ryan
Buchner)
* Add actually_store tag to misaligned_store function (Ryan Buchner)
* Modify store_func to throw fault if misaligned and
require_alignment=true (Ryan Buchner)
* Set require alignment to true on the 'fake' store in amo_func. (Ryan
Buchner)
* Add require_alignment tag to store_func (Ryan Buchner)
* Add ns16550 serial device emulation (Anup Patel)
* Add PLIC emulation (Anup Patel)
* Add an abstract interrupt controller interface (Anup Patel)
* add support for overlap instructions (Weiwei Li)
* fix style problems in decode.h and processor.cc (Weiwei Li)
* Adjust indentation in store_slow_path and store_func (Ryan Buchner)
* Skip storing in store_func if actually_store is false, add a fake
store at start of AMO. (Ryan Buchner)
* Add actually_store tag to store_func and store_slow_path (Ryan
Buchner)
* Move real_time_clint into cfg_t (Rupert Swarbrick)
* Move varch into cfg_t (Rupert Swarbrick)
* Remove nprocs from cfg_t (Rupert Swarbrick)
* Move hartids into cfg_t (Rupert Swarbrick)
* Move the "default hartids" logic from sim.cc into spike.cc (Rupert
Swarbrick)
* Slightly refactor --hartids parsing in spike.cc (Rupert Swarbrick)
* Move start_pc into cfg_t (Rupert Swarbrick)
* Fix debug messages about invalid pmpregions/mmu-types (Rupert
Swarbrick)
* Change processor_t to hold a pointer to an isa_parser_t
(riscv/riscv-isa-sim#973) (Rupert Swarbrick)
* Split mem layout computation in spike.cc (riscv/riscv-isa-sim#957)
(Rupert Swarbrick)
* Fix hgatp CSR write (Anup Patel)
* Adjust the access index of vs2 to zero in vmv_x_s.h (riscv/riscv-
isa-sim#969) (Brandon Wu)
* Replaced vector loop compare body with newly defined macro (4vtomat)
* Adding new macro to replace repetitive code (4vtomat)
* Rename processor_t::set_csr to put_csr to fix build on RISC-V
(Andrew Waterman)
* Fix build of dtm.cc on RISC-V targets (Andrew Waterman)
* Pass ref instead of pointer to trigger_updated() (Tim Newsome)
* Add const to pointers where possible. (Tim Newsome)
* Add module_t::~module_t() (Tim Newsome)
* mmu: support asid/vmid (riscv/riscv-isa-sim#928) (Chih-Min Chao)
* Tick devices even when tohost != 0 (Andrew Waterman)
* Make triggers a vector of trigger_t. (Tim Newsome)
* Abstract away access to load/store/execute bits. (Tim Newsome)
* Make trigger_t::tdata{1,2}_{read,write} virtuals (Tim Newsome)
* Make chain into chain() for all triggers. (Tim Newsome)
* Make triggers::module_t::triggers private. (Tim Newsome)
* Move num_triggers knowledge into triggers.h (Tim Newsome)
* Don't access triggers vector directly from csrs.cc. (Tim Newsome)
* Move trigger match logic into triggers.cc (Tim Newsome)
* module_t::trigger_match -> memory_access_match (Tim Newsome)
* Move mcontrol match logic into mcontrol_t. (Tim Newsome)
* trigger_matched_t -> triggers::matched_t (Tim Newsome)
* Give triggers::module_t its own processor_t* (Tim Newsome)
* Move trigger_match() into triggers. (Tim Newsome)
* Move tdata2 logic into trigger. (Tim Newsome)
* Turn unsupported mcontrol.match into a supported one. (Tim Newsome)
* V in misa implies FD (Mark Fedorov)
* Make misa.V writable (Mark Fedorov)
* Since ca08503 this code only runs at reset, so no longer depends on
misa.V being constant (Mark Fedorov)
* Make misa.Q writable (Mark Fedorov)
* Refactor misa masking (Mark Fedorov)
* update dts.cc to make sv57 default maximum paging mode (riscv/riscv-
isa-sim#962) (Alenkruth Murali)
* Move tdata1 write logic into triggers. (Tim Newsome)
* Move tdata1 read logic into triggers.cc. (Tim Newsome)
* Make a few processor_t members const. (Tim Newsome)
* Move tdata2 into mcontrol_t (Tim Newsome)
* Replace state.mcontrol with TM.triggers. (Tim Newsome)
* Create trigger_t class. (Tim Newsome)
* mcontrol_match_t -> mcontrol_t::match_t (Tim Newsome)
* Move mcontrol_t and mcontrol_match_t into triggers (Tim Newsome)
* mcontrol_action_t -> triggers::action_t (Tim Newsome)
* trigger_operation_t -> triggers::operation_t (Tim Newsome)
* Create triggers.cc, triggers.h. (Tim Newsome)
* Implement Sv57 and Sv57x4 translation modes (Andrew Waterman)
* Refactor switch statement for DRY and readability (Andrew Waterman)
* Don't allow hgatp.MODE to be set to Sv48x4 unless implemented
(Andrew Waterman)
* Fix start byte for vmv<nf>r.v (riscv/riscv-isa-sim#959) (liweiwei90)
* Split isa_parser_t out of processor.* and into its own file
(riscv/riscv-isa-sim#955) (Rupert Swarbrick)
* Fold priv parameter into cfg_t (Rupert Swarbrick)
* Fold isa parameter into cfg_t (Rupert Swarbrick)
* Fold nprocs parameter into cfg_t (Rupert Swarbrick)
* Fold bootargs parameter in the new cfg_t type (Rupert Swarbrick)
* Initial step towards factoring out command line configuration
(Rupert Swarbrick)
* Compile using C++17 standard (Scott Johnson)
* Improve error message when HTIF accesses invalid memory (Andrew
Waterman)
* Don't respond to invalid HTIF operations with assertion failures
(Andrew Waterman)
* Inline trap_t methods so they can be used in fesvr code (Andrew
Waterman)
* Raise illegal (not virtual) instruction exception on counter writes
(riscv/riscv-isa-sim#951) (Andrew Waterman)
* Inline most implicit accesses to fflags/frm (Andrew Waterman)
* Refer to concrete members in sstatus_csr_t::dirty() (Andrew
Waterman)
* Speed up sstatus_csr_t::dirty(); remove redundant log entries
(Andrew Waterman)
* Rewrite sstatus_csr_t::enabled() for higher performance (Andrew
Waterman)
* Give concrete types to fields of sstatus_proxy_csr_t (Andrew
Waterman)
* Give concrete types to fields of sstatus_csr_t (Andrew Waterman)
* Allow sstatus_proxy_csr_t::read() to be inlined (Andrew Waterman)
* Allow mstatus_csr_t::read() to be inlined (Andrew Waterman)
* Allow vsstatus_csr_t::read() to be inlined (Andrew Waterman)
* Move sstatus_proxy_csr_t defn below that of mstatus_csr_t (Andrew
Waterman)
* Fix perf regression from CSR refactoring (riscv/riscv-isa-sim#949)
(Andrew Waterman)
* Construct an isa_parser_t and pass it to processor_t constructor
(Rupert Swarbrick)
* Incorporate supported privilege levels into isa_parser_t
(riscv/riscv-isa-sim#940) (Rupert Swarbrick)
* Update debug_defines.h (riscv/riscv-isa-sim#942) (Tim Newsome)
* Change some methods to take a const isa_parser_t (riscv/riscv-isa-
sim#939) (Rupert Swarbrick)
* fill rv32e and rv64e function for instructions of rocc and customext
(Weiwei Li)
* perform hstatus probe/update for sret only when H extension enabled.
(riscv/riscv-isa-sim#934) (Neel Gala)
* add missed extensions specified by '--extension' to
custom_extensions (Weiwei Li)
* clean up for rv32e_unratified. (Neel Gala)
* clean up the the arch-test directory to avoid copypasta (Neel Gala)
* adding ports to run F, D and E extension architectural tests on
spike (Neel Gala)
* pmp: dts: handle the absence of mmu and pmp in dts (Chih-Min Chao)
* csr: hyper: fix mstatus.mpp after mret (Chih-Min Chao)
* csr: mstatus.sxl and mstatus.uxl are zero in rv32 (Chih-Min Chao)
* perf: refine csr accessibility checking (Chih-Min Chao)
* rvv: add missing elen checking for some ldst (riscv/riscv-isa-
sim#927) (Chih-Min Chao)
* Avoid an unnecessary strcpy (riscv/riscv-isa-sim#925) (Rupert
Swarbrick)
* Make comment more germane (Andrew Waterman)
* Documentation: Cache block size for CMO operations default 64
(riscv/riscv-isa-sim#923) (John Ingalls)
* Split out MINSTRET and MCYCLE (Rupert Swarbrick)
* Rename minstret CSR classes to something more general (Rupert
Swarbrick)
* Don't instantiate a CLINT if there is none in the device config
(riscv/riscv-isa-sim#921) (Rupert Swarbrick)
* Add simple error checking to DTB parsing code (Rupert Swarbrick)
* Remove duplicate DTB load step (Rupert Swarbrick)
* Remove disasm.cc/disasm.h from riscv subproject (riscv/riscv-isa-
sim#919) (Rupert Swarbrick)
* Split Xbitmanip into its proposed component extensions (riscv/riscv-
isa-sim#918) (Rupert Swarbrick)
* Improve fallback disassembly for disabled ISA strings (Andrew
Waterman)
* Don't require __int128 support in isa_parser_t (Andrew Waterman)
* Fix disassembly of vmadc.vi and friends (Andrew Waterman)
* update README (liweiwei)
* add disasm support for cmo instructions (liweiwei)
* add instructions function for cmo (liweiwei)
* add clean_invalidate function for caches (liweiwei)
* add isa string, csr support for cmo extensions (liweiwei)
* add blocksz parameter to specify the cache block size for CBO
operations (liweiwei)
* add disas support for zfinx, zdinx and zhinx{min} (Weiwei Li)
* Bind disas for instructions with the isa support (Weiwei Li)
* Use unified ISA-string processing in spike-dasm and spike (Weiwei
Li)
* Add more assertion for fcvt (riscv/riscv-isa-sim#910) (Yueh-Ting
(eop) Chen)
* fix redefinition of CSR_MCONTEXT and CSR_SCONTEXT (Weiwei Li)
* Fix HINVAL.VVMA and HINVAL.GVMA opcodes (Andrew Waterman)
It counts and saves the saturation bits in D flip-flops for
the ASIC version and in a three-port asynchronous read memory
for the FPGA version.
FPGA flushing is not supported because the frontend module
flushing signal is not connected.
