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Author SHA1 Message Date
André Sintzoff
961c4f0948
Merge pull request #2114 from 10x-Engineers/arch-test-update 
Updated riscv-arch-test suites
 2023-08-08 09:42:05 +02:00
André Sintzoff
aabc34c5d2
Merge pull request #2111 from ThalesSiliconSecurity/covxif 
CVXIF : Filter cross coverage for commit interface
 2023-08-08 09:23:37 +02:00
Fatima Saleem
3e060e454e edited the path of spike folder 2023-08-07 22:12:16 +05:00
Fatima Saleem
7489e30889 updated hash of cva6 and arch-tests 2023-08-07 22:12:04 +05:00
Ayoub Jalali
e1ab520510 CVXIF : Filter cross coverage for commit interface 
no need to create bins when commit valid is low
 2023-08-07 17:13:57 +02:00
André Sintzoff
54747422ef
Merge pull request #2103 from ThalesSiliconSecurity/spike-yield-load-reservation 
[SPIKE] sim.cc: do not yield load reservation on single core
 2023-08-07 08:37:43 +02:00
André Sintzoff
9fca53c342 [SPIKE] sim.cc: do not yield load reservation on single core 
to have same behaviour on spike and on RTL with one core,
do not yield load reservation at the end of each block of
INTERLEAVE steps


Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
 2023-08-04 16:55:28 +02:00
André Sintzoff
a977cc0629
Merge pull request #2076 from ThalesSiliconSecurity/dev/fix-cva6-version 
fix: display correct CVA6 version
 2023-08-01 14:18:28 +02:00
André Sintzoff
e664b3f174
Merge pull request #2094 from ThalesSiliconSecurity/covxif 
CVXIF : Filter exception cross if exc=0
 2023-08-01 13:46:42 +02:00
Côme Allart
652d439308 fix: display correct CVA6 version 2023-08-01 10:42:29 +02:00
Ayoub Jalali
4a4b4a3e0e CVXIF : Filter exception cross if exc=0 2023-07-31 11:15:03 +02:00
André Sintzoff
b5ab374695
Merge pull request #1895 from AyoubJalali/decoder/isa 
Decoder for some C instructions
 2023-07-28 16:36:54 +02:00
André Sintzoff
2db59e20b7
Merge pull request #2091 from ThalesSiliconSecurity/ci-rework-stages 
ci: rework and document
 2023-07-28 15:44:29 +02:00
Mike Thompson
99ce43c6c1
Merge pull request #2077 from ThalesSiliconSecurity/isafix 
ISACOV : remove rs2_toggle from c.lw cover group (fix issue #2073)
 2023-07-28 09:14:32 -04:00
André Sintzoff
3d661dce41
Merge pull request #2092 from AyoubJalali/fix_cva6 
cva6.py: update config_pkg_generator.py path

on cva6 repository, config_pkg_generator.py is moved to util directory since PR1018 (dc103cd)
 2023-07-28 13:33:52 +02:00
Ayoub Jalali
09b1a187d0 cva6.py : Fix config_pkg_generator.py path 2023-07-28 12:35:58 +02:00
Côme Allart
d578079139 fix: update location of config_pkg_generator.py 
According to https://github.com/openhwgroup/cva6/pull/1318
 2023-07-28 12:22:52 +02:00
Côme Allart
bbd77e0d2a ci: update hwconfig job as A was added to cv32a60x 2023-07-28 11:51:06 +02:00
Côme Allart
ac33bd7200 ci: use only cv32a60x target on fpga 2023-07-27 16:40:07 +02:00
Côme Allart
286445397c ci: document the CI structure 2023-07-27 10:14:31 +02:00
Côme Allart
5944f1d581 ci: refactor job descriptions 
Each job needs less code in cva6.yml

It also fixes an issue in CVV pipelines, where the CVA6 hash in the
dashboard was not the one used in some jobs of the pipeline.
 2023-07-27 10:14:31 +02:00
Côme Allart
7a040e74c6 ci: rely on stages more than needs relationships 
"needs" relationships are tricky as they bypass stage ordering.

For instance, "initjob" was useless, which was a bug.
 2023-07-27 10:14:31 +02:00
JeanRochCoulon
fa24d9f122
Merge pull request #2078 from ThalesSiliconSecurity/test_isa 
ISACOV : switch beq instruction register
 2023-07-26 14:56:20 +02:00
JeanRochCoulon
60a3c99451
Merge pull request #2084 from ThalesSiliconSecurity/gcc13 
Add GCC version check and README to build GCC.
 2023-07-26 14:55:17 +02:00
Corentin MARAIS
a8c304c95b README.md update 2023-07-26 14:37:44 +02:00
Corentin MARAIS
8225252923 Switch to gcc 13 with gcc version check. 2023-07-26 12:21:02 +02:00
Ayoub Jalali
44343f771a ISACOV : switch beq instruction register 2023-07-25 12:37:44 +02:00
Ayoub Jalali
7d51dca907 ISACOV : add CL instruction decode imm 2023-07-25 11:39:52 +02:00
Ayoub Jalali
bb2331d5a1 ISACOV : Fix cover group for rx 3-bit encoding compressed instruction 2023-07-25 11:39:52 +02:00
Ayoub Jalali
bb89a319d0 ISACOV : Create decoder for some Compressed instructions 2023-07-25 11:39:52 +02:00
JeanRochCoulon
b623e14a8f
Merge pull request #2075 from ThalesSiliconSecurity/feature/csr-tests-gcc-13 
A parameter called --isa_extension has been added in cva6.py. Depending on the set of instruction the user want to use while compiling/executing a code (assembly/c/elf) the user can choose the extension to enable via this argument. i,m,a,f,d,c,g,v are not supposed to be specified here only z_, s_, or x_ extensions can be added via this argument. This argument is set to zicsr by default.

Ex: python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a60x --iss= --isa_extension=zicsr,zbb

In this example, the extension zicsr and zbb has been added to the isa initially associated to the target cv32a60x.
 2023-07-24 18:51:11 +02:00
Ayoub Jalali
589b3005b8 ISACOV : remove rs2_toggle from c.lw cover group (fix issue #2073) 
Signed-off-by: Ayoub Jalali <ayoub.jalali@external.thalesgroup.com>
 2023-07-24 16:20:15 +02:00
Corentin MARAIS
69603f71b1 Switch to GCC 13 
Implementation of a new argument isa_extension in cva6.py to switch to gcc 13.1.0.
This argument includes the specific extensions to add to the isa for compilation.
It takes zicsr by default (extension to enable csr instructions).
Bugs fixed on: dv-riscv-compliance and dv-riscv-tests (need of enabling zifencei also), smoke_test (use of one linker instead of two).
 2023-07-24 15:39:33 +02:00
JeanRochCoulon
674961b542
Merge pull request #2071 from ThalesSiliconSecurity/cvvdev/dev/params 
Define AXI as cva6 input parameters
 2023-07-24 10:35:05 +02:00
JeanRochCoulon
e96d391890
Merge pull request #2072 from ThalesSiliconSecurity/fixco 
HOTFIX : Fix a cross in cvxif agent coverage model
 2023-07-22 23:01:36 +02:00
Jean-Roch Coulon
bbbe86071b Merge axi and l15 into noc 2023-07-21 17:35:07 +02:00
Jean-Roch Coulon
fb7f3089a6 move ariane_axi_pkg.sv from core to corev_apu 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-21 16:00:04 +02:00
Jean-Roch Coulon
d071ec6278 Move axi_intf.sv from core to corev_apu 2023-07-21 16:00:04 +02:00
Jean-Roch Coulon
7f781bb991 add axi parameter to cfg 2023-07-21 15:59:57 +02:00
Ayoub Jalali
fec26ce792 HOTFIX : Removing rd from cross 2023-07-21 15:38:51 +02:00
André Sintzoff
8544808225
Merge pull request #2065 from ThalesSiliconSecurity/cvvdev/dev/rvfi4 
Use CVA6Cfg as cva6 parameter
 2023-07-20 13:37:25 +02:00
Jean-Roch Coulon
c964710244 Use CVA6Cfg as cva6 parameter 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-20 09:37:53 +02:00
JeanRochCoulon
034d30d30a
Merge pull request #2062 from ThalesSiliconSecurity/feature/reduceCI 
Make some synthesis CI jobs manual
 2023-07-19 16:32:37 +02:00
Jean-Roch Coulon
17c192682e Make some synthesis CI jobs manual 
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-19 12:08:16 +02:00
JeanRochCoulon
a736753ef7
Merge pull request #2019 from ThalesSiliconSecurity/cvvdev/dev/rvfi0 
Define RVFI as cva6 parameter
 2023-07-19 08:22:58 +02:00
JeanRochCoulon
706830aae0
Merge pull request #2063 from ThalesSiliconSecurity/fixcov 
Isacov_status.rst: fix RVFI limitation description
 2023-07-18 22:49:53 +02:00
Ayoub Jalali
d5ec412732 HOTFIX : Correct the sentence 2023-07-18 17:21:01 +02:00
Jean-Roch Coulon
bd4de7ea44 Define RVFI as cva6 parameter 
Change police style by adopting Camel style for parameters

Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
 2023-07-17 23:44:32 +02:00
Guillaume Chauvon
033669025f [HOTFIX CI] Make all jobs requiring Spike dependents on build_tools job 
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
 2023-07-17 23:44:32 +02:00
JeanRochCoulon
4b455958de [HOT FIX] Update Spike artifact to fix Thales CI 
The Spike artifact generated by Spike job must be move to be used by other jobs. Otherwise the Spike build generates a disk full.
 2023-07-17 23:44:32 +02:00