Michael Schaffner
cca0d66fab
switch to common_cells repo, remove redundant files, cleanup + benderize
2018-08-24 16:22:49 +02:00
Michael Schaffner
4f7bd54065
add fpga-support submodule, exchange srams with inferrable blockrams, remove flat byte enables
...
switch icache to inferrable blockrams
exchange sram with regfile
switched sram to sram_wrapper in testharness
replace dirty/valid sram with regfile
replace behav_sram with fpga inferrable ram
remove flat byte enables
fix in makefile
add reset to valid regs
2018-08-24 12:23:50 +02:00
Michael Schaffner
5c5e37fc25
small byte enable fixes in dm
2018-08-24 12:23:50 +02:00
Michael Schaffner
5e7734559f
fix #78
2018-08-22 17:21:54 +02:00
Michael Schaffner
8e89f62181
⚡ restructure travis and gitlab-ci flow scripts and make targets
...
* fix typo in signal naming and make axi_adapter questa-sim compliant
2018-08-22 17:21:42 +02:00
Florian Zaruba
238dbf8f04
Merge remote-tracking branch 'origin' into ariane_next
2018-08-21 20:22:31 -07:00
msfschaffner
8f0b388ecb
⚡ Cache hierarchy and LSU load unit optimizations
...
* ♻️ restructure hierarchy (move dcache out into ariane/std_cache_subsystem)
* update uvm-components submodule
* ♻️ switch to newer (and better) fifo implementation. redesign of lsu_arbiter to improve on timing.
* ♻️ restructure hierarchy (move dcache out into ariane/std_cache_subsystem)
* ♻️ move icache out to cache_subsystem. connect icache performance counter.
* ♻️ code cleanup
* ♻️ rewrote sign extension mux to decrease comb. delay
* provision additional logic for FLW, FLH, FLB in load_unit
* code cleanup, add efficient RR arbiter with lookahead capability
* change portnames in ariane_wrapped.sv for verilator TB
2018-08-18 11:03:09 -07:00
Florian Zaruba
38fb57ea68
Merge remote-tracking branch 'origin' into ariane_next
2018-08-14 08:52:21 -07:00
Florian Zaruba
fc6d7d2f82
Merge pull request #74 from pulp-platform/zarubaf-issue-72
...
Fix #72
2018-08-14 08:51:04 -07:00
Florian Zaruba
be927f77a9
Guard cover and asserts with `ifdef
2018-08-14 08:17:31 -07:00
Florian Zaruba
29d5be5716
Fix #72
...
Add cover directive and assertion on the cache interface.
2018-08-13 10:08:17 -07:00
Florian Zaruba
8b7d4bd61a
✨ Implement SBA business logic
2018-08-01 23:09:59 -07:00
Florian Zaruba
367bc46046
Add AXI Master module to SBA
2018-08-01 21:56:18 -07:00
Florian Zaruba
dc9442356c
♻️ Re-factor AXI master adapter
2018-08-01 21:43:49 -07:00
Florian Zaruba
e71da32bcc
Add SBA stub module
2018-08-01 21:34:20 -07:00
Florian Zaruba
9ed2a25dc1
✨ Add SBA CSRs to debug module
2018-08-01 21:20:40 -07:00
Florian Zaruba
5a2a86f333
🚨 Fix some verilator lint warnings
2018-08-01 20:25:15 -07:00
Florian Zaruba
bba2485c90
Add msip field
2018-08-01 18:07:42 -07:00
Florian Zaruba
af638dc034
📝 Add brief documentation about CLINT
2018-08-01 17:43:34 -07:00
Florian Zaruba
f752dfa0d9
Re-name ariane_timer to clint
2018-08-01 17:41:39 -07:00
Florian Zaruba
1949b30304
Add ariane_timer as src/clint
2018-08-01 17:38:28 -07:00
Florian Zaruba
6c02039ca1
Move to src director
2018-08-01 17:35:12 -07:00
Florian Zaruba
9d82195d90
Move files to clint subfolder
2018-08-01 17:33:59 -07:00
Florian Zaruba
398bcce81b
Fix unaligned tval issue
2018-08-01 17:30:56 -07:00
Florian Zaruba
929ef3bb54
Update device tree and fix possible LSU deadlock
2018-08-02 02:02:47 +02:00
Florian Zaruba
c6b6213358
📝 Update README.md
2018-08-02 02:02:30 +02:00
Florian Zaruba
0e80b31191
Merge branch 'master' into ariane_next
2018-08-01 00:35:42 -07:00
Florian Zaruba
72d62f93e6
Include basic device tree for standalone simulation
2018-08-01 00:34:23 -07:00
Florian Zaruba
a19318201a
🎨 Fix #56
2018-07-31 21:40:20 -07:00
Florian Zaruba
5ce476124b
🐛 Fix #71
2018-07-31 21:38:27 -07:00
Florian Zaruba
bee159b226
Merge pull request #64 from pulp-platform/riscv-compliant-debug
...
This PR adds RISC-V compliant debug. Verilator and Questa simulation have been aligned in terms of HTIF communication. Basic debug tests are passing. CI is slow but passing.
2018-07-31 21:33:14 -07:00
Florian Zaruba
85300f8b75
Merge branch 'riscv-compliant-debug' of github.com:pulp-platform/ariane into riscv-compliant-debug
2018-08-01 03:30:46 +02:00
Florian Zaruba
1db6d9158a
♻️ Move dcsr_t definition to riscv pkg
2018-08-01 03:29:45 +02:00
Florian Zaruba
064c0a0ac7
🔥 Remove legacy if stage
2018-08-01 02:59:08 +02:00
Florian Zaruba
57b1567b09
Merge branch 'ariane_next' into riscv-compliant-debug
2018-07-31 17:20:28 -07:00
Florian Zaruba
126520bf8f
⚡ Make tracing optional
2018-08-01 02:17:17 +02:00
Florian Zaruba
f24455e7f9
🎨 Move riscv definitions to riscv package
2018-08-01 02:06:26 +02:00
Florian Zaruba
ed58d6f4cc
🐛 Fix #69 , trap in U-mode on sfence.vma
2018-08-01 01:42:31 +02:00
Florian Zaruba
6c28c9610e
Remove time reference from testbench
2018-08-01 01:41:19 +02:00
Florian Zaruba
622a09779a
🎨 Flatten tb submodule
2018-08-01 01:39:01 +02:00
Florian Zaruba
319ed5632e
🔥 Remove timer, CSR will trap on access
2018-08-01 01:25:05 +02:00
Florian Zaruba
5885de8d37
🎨 Remove section about unit tests
2018-08-01 01:20:02 +02:00
Florian Zaruba
25995e9524
🎨 Celan-up interface folder
2018-08-01 01:19:25 +02:00
Florian Zaruba
e423793858
🎨 Remove axi2per
2018-08-01 01:17:41 +02:00
Florian Zaruba
85f6792241
🔥 Removed axi2per submodule
2018-08-01 01:15:28 +02:00
Florian Zaruba
37c9015120
🎨 Clean-up README and rom comments
2018-08-01 01:09:28 +02:00
Florian Zaruba
c01601d7a4
🐛 Fixes in debug module
...
- Fix single-step address caluclation (not enough bits for adder)
- Fix resumeack and resumereq protocol
- Fix tinfo throwing an illegal instruction exception upon r/w
2018-07-31 08:05:31 +02:00
Florian Zaruba
82fb37930f
Add trigger CSR stubs as defined in spec 0.13
2018-07-30 17:29:37 -07:00
Florian Zaruba
3452d79fc3
Set default trap vector to boot_adr + 'h40
2018-07-31 01:14:53 +02:00
Florian Zaruba
b21e43bc21
👾 Fix synthesis warning, update debug files
2018-07-31 01:12:18 +02:00
