Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Guillaume Chauvon
13a4a092ab
Check that User mode is enable to set MPP to U-mode ( fix #1756 ) ( #1781 )
2024-01-25 10:05:57 +01:00
Guillaume Chauvon
e0ca60169b
Fix path for vcs init_testharness.do ( #1780 )
2024-01-24 17:49:02 +01:00
Jalali
358a73a07d
Enable zcb extension into cva6 UVM env ( #1777 )
2024-01-24 15:37:18 +00:00
dependabot[bot]
6568b18a54
Bump verif/core-v-verif from 0ea56b3 to 752e67f ( #1776 )
2024-01-23 16:01:03 +01:00
Jalali
cabbaf690d
Exclude cva6_rvfi_combi module from Code coverage ( #1773 )
2024-01-22 17:16:02 +01:00
Côme
5742d2abc9
fix: add missing parameters in cva6_rvfi.sv ( #1771 )
2024-01-19 16:19:34 +00:00
Siris Li
ef5e378c93
Fix bug in install-spike.sh ( #1763 )
2024-01-18 23:32:32 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
MarioOpenHWGroup
8b6e8295f8
Add priv level to cva6.py and fix smoke-tests ( #1768 )
2024-01-17 23:14:19 +01:00
Michael Platzer
78111aa5eb
config_pkg/csr_regfile: Add PMP entry rst vals & RO option ( #1769 )
...
This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
2024-01-17 17:41:38 +01:00
Michael Platzer
37427a75a9
acc_dispatcher: Add ld/st priv mode, sum & PMP iface ( #1767 )
2024-01-17 00:43:21 +01:00
dependabot[bot]
284200dfc9
Bump verif/core-v-verif from dfa7c47 to 0ea56b3 ( #1764 )
2024-01-15 20:44:47 +01:00
Domenic Wüthrich
49cdc9045c
Break timing loop in axi adapter arbiter of WB cache ( #1761 )
2024-01-15 15:18:11 +01:00
André Sintzoff
3afe870d78
csr_regfile.sv: add RVB field for MISA ( fix #1734 ) ( #1760 )
2024-01-15 14:34:25 +01:00
Guillaume Chauvon
969c91eefa
Check that loaded elf segment does not overlap on last loaded address ( #1755 )
2024-01-11 11:37:00 +01:00
André Sintzoff
dc634c61de
doc: update MVENDORID CSR value ( fix #1735 ) ( #1753 )
2024-01-10 11:30:48 +01:00
JeanRochCoulon
88ab5a94dc
Update contibuting.md: contribution shall not impact code coverage ( #1752 )
2024-01-09 15:38:30 +01:00
Jalali
4279cc0f6e
Fix CSR coverage model & HVP ( #1751 )
2024-01-09 11:55:09 +01:00
andriami
59177e37d3
Reformat the ariane_pkg to fix synthesis crash ( #1750 )
...
Modify ariane_pkg.sv following issue #1726 .
2024-01-08 20:02:07 +01:00
dependabot[bot]
c430c6c34b
Bump verif/core-v-verif from 4da8b11 to dfa7c47 ( #1747 )
2024-01-05 17:45:39 +01:00
Jalali
4cd5c4a7e8
Add overflow counter test & fix reset value ( #1746 )
2024-01-05 13:29:48 +01:00
dependabot[bot]
cd0ade199c
Bump verif/core-v-verif from 18c9d28 to 4da8b11 ( #1745 )
2024-01-04 10:43:32 +01:00
valentinThomazic
706daa0a3b
removed the usage of install-cva6.sh and add setup-env.sh ( #1741 )
2024-01-03 13:42:23 +01:00
JeanRochCoulon
72b855672e
Fix inhibit impact on MCYCLE csr ( #1743 )
2024-01-03 12:20:07 +01:00
JeanRochCoulon
2708df998d
Rename cva6 ( #1723 )
2024-01-02 12:05:07 +01:00
valentinThomazic
4feab99254
Add prerequisites to README ( #1738 )
2023-12-27 16:36:23 +01:00
Jérôme Quévremont
6e79e20cc6
UM: Part number + reshuffled Zb* RV32/RV64 instructions ( #1733 )
2023-12-21 17:23:14 +01:00
Anouar
8aca3438ee
Added CSR covegroups for read and write operations, hvp updated accordantly ( #1706 )
2023-12-21 13:54:20 +01:00
Yaotian Liu
e6a0d9e06a
fix: extra space in command ( #1730 )
2023-12-21 06:29:52 +01:00
Jérôme Quévremont
5716b378da
Integrated Zb* in user manual (index.rst) ( #1728 )
2023-12-20 08:39:10 +01:00
Gull Ahmed
b3139eaae0
update Zb* docs ( #1721 )
2023-12-19 17:46:23 +01:00
Côme
2b33926900
fix: exception on misaligned branch if no RVC ( #1719 )
2023-12-19 10:03:11 +01:00
Jérôme Quévremont
4103b2ccdc
Changing part number in user manual ( #1718 )
2023-12-18 16:32:30 +01:00
Gull Ahmed
8c14b6aa4a
resolving issue #1613 ( #1714 )
2023-12-17 17:59:22 +01:00
Jérôme Quévremont
ad570000b3
Remove fixed-time division (ISA-110) ( #1670 )
...
After further investigation, the feature is not needed for security application.
For safety applications, variable-time division is only one of several sources of unpredictability and it does not make no real sense to fix it.
2023-12-15 14:52:10 +01:00
JeanRochCoulon
5e9cb5d64e
Designdoc ( #1713 )
...
* rename csr files
* Revisit the design specification skeleton
2023-12-15 14:51:32 +01:00
Florian Zaruba
344c1db4b8
Clarify pmpcfgX on illegal write combination ( fixes #1694 ) ( #1711 )
2023-12-14 15:48:40 +01:00
Florian Zaruba
8146c96d86
csr: Implement menvcfg ( #1653 )
2023-12-14 15:25:38 +01:00
Côme
fab3255823
refactor(decoder): simplify interrupt indexing ( #1709 )
2023-12-14 14:36:17 +01:00
Côme
4e3f470a75
ci: report embedded CoreMark/MHz score ( #1710 )
2023-12-14 13:29:31 +01:00
Jérôme Quévremont
6e41bc8b52
Updated user manual to address several configuration (second pass) ( #1696 )
2023-12-13 10:10:31 +01:00
Jérôme Quévremont
98c776dc2d
Updated user manual to address several configuration (first pass) ( #1685 )
2023-12-13 10:08:40 +01:00
AEzzejjari
738d53af1c
Code coverage: condition RTL With parameters ( #1703 )
2023-12-13 07:52:47 +01:00
MarioOpenHWGroup
e5a0993ef9
Verilator Tandem Support ( #1702 )
2023-12-12 18:49:49 +01:00
JeanRochCoulon
d2453163eb
Update embedded config to improve trade-off performance gate count ( #1701 )
2023-12-12 18:43:09 +01:00
MarioOpenHWGroup
809bcf4ed0
Update verilator to v5.018 ( #1699 )
2023-12-12 14:02:59 +01:00
dependabot[bot]
d812c03712
Bump verif/core-v-verif from 6779193 to 76b887f ( #1698 )
2023-12-11 22:16:44 +01:00
Guillaume Chauvon
cef7e573c4
Set StallRandom I/O to 0 to gain performance on vcs-testharness bench ( #1695 )
2023-12-11 18:53:27 +01:00
André Sintzoff
a837e94eac
CONTRIBUTING.md: add verible-verilog-format ( #1689 )
2023-12-08 19:59:40 +01:00
