These signals do not need to be generated by the WB FSM inside the ID
stage and be fed back into the decoder. They simply depend on whether
the instruction is new (we execute for the first cycle) or not.
The EX block actually signals when its output is valid, and not when it
is ready to accept new input. The LSU valid signal is not needed inside
the EX block and can thus be fed directly to the ID stage.
This commit makes sure that if any instruction is detected as being
illegal inside the decoder, the decoder does not set the control
signals to let the illegal instruction affect the register file,
LSU, EX, WB, CSRs. Previously, this was only the case for some but
but not all instructions.
Note that this is not sufficient to prevent instructions detected
as illegal elsewhere from affecting the processor state. For example,
when using RV32E, an instruction can be detected to use unavailable
registers outside the decoder in the ID stage. But it is cleaner to
handle all illegal instructions detected in the decoder similarly.
* Remove all local patches
* Update google_riscv-dv to 00739df
Update code from upstream repository https://github.com/google/riscv-
dv to revision 00739df0ec744986934097bebcde3ebf5a4fdf81
* Merge pull request #30 from google/dev (taoliug)
* Fix LSF options (Tao Liu)
* Refactoring to make extension easier (Tao Liu)
* Merge pull request #29 from google/dev (taoliug)
* Add a sample program (Tao Liu)
* Merge pull request #28 from google/dev (taoliug)
* Move riscv_core_setting to a separate folder (Tao Liu)
* Merge pull request #27 from google/dev (taoliug)
* Add ebreak/wfi test, more regression control (Tao Liu)
* Merge pull request #26 from google/dev (taoliug)
* Add support for GPR based comparison (Tao Liu)
* Add ibex extensions for riscv_dv
For exceptions, the Ibex always jumps to the trap vector base address
specified in `mtvec`. The exception cause is specified in `mcause` with
possibly additional information in `mtval`.
Interrupts are handled in vectored mode as before.
`mtval` can provide additional information to trap handlers.
In case of load/store errors, it holds the failing address.
For illegal instruction exceptions, it holds the illegal instruction.
This operation only depends on the LSU detecting a misaligned address.
Previously, the mux control was scattered across ID stage, controller
and decoder. With this commit, all the relevant code for this operation
is moved into the ID stage and also streamlined.
Verilator displays the following lint warnings:
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv💯 Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'RV32E' generates 1 bits.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv:103: Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'RV32M' generates 1 bits.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_cs_registers.sv:108: Operator SHIFTL expects 32 bits on the LHS, but LHS's VARREF 'MXL' generates 2 bits.
%Warning-WIDTH: ../src/lowrisc_ibex_ibex_0.1/rtl/ibex_register_file_ff.sv:63: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'waddr_a_i' generates 5 bits.
It's not quite clear (to me) from reading the SV spec if this is a bug
in Verilator lint, or if this is actually a code bug.
Alternative proposal for #92
Performance counters are an optional feature. Disable them by default to
avoid users having them enabled unknowingly and paying the (rather
large) area price for it.
The core handles unaligned instruction fetches by doing two separate
word-aligned instruction fetches. Without this commit, the core can
still output addresses which are not word aligned and relies on the
memory to ignore the LSBs of the address. This is not safe.
The core handles unaligned accesses by doing two separate word-aligned
accesses. Without this commit, the core can still output addresses
which are not word aligned and relies on the memory to ignore the LSBs
of the address. This is not safe.
Without this commit, the performance counters mhpmcounter3(h)-
mhpmcounter31(h) are optimized away during synthesis due to
`X`-values in the address decoder masks. This commit replaces
these masks with offsets and instead masks the input address
before comparison.
To enable the synthesizer optimizing away unused counters,
the masks for these counters are set to zero.
Without this change, the core can continue to write CSRs during multiple
subsequent clock cycles when being stalled. This can corrupt CSR (e.g.
performance counters).
This commit helps to make the README.md the main entry point into the
Ibex world. It does so by updating it and including additional
references to a style guide, a guide on how to write commit messages,
references to our Zulip chat and the original Zero-riscy paper.
