udinator
f339f6b96b
[DV] Test nested interrupts ( #560 )
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Signed-off-by: Udi <udij@google.com>
2020-01-23 15:11:54 -08:00
udinator
9d7b07f0f7
[DV] Add test to assert interrupts during debug execution ( #524 )
2020-01-16 11:43:44 -08:00
udinator
80067b077c
[DV] Add riscv-dv target for ML ( #556 )
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Signed-off-by: Udi <udij@google.com>
2020-01-14 14:11:57 -08:00
udinator
0c55214380
Enable coverage collection and merging for Incisive sims ( #552 )
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Signed-off-by: Udi <udij@google.com>
2020-01-10 16:46:33 -08:00
udinator
b318b96964
[DV] update ibex log parsing to match new riscv-dv csv format ( #547 )
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Signed-off-by: Udi <udij@google.com>
2020-01-09 14:46:50 -08:00
Pirmin Vogel
0778008f33
[rtl] Remove X assignments, add SVAs for selector signals
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This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2019-12-20 10:09:09 +01:00
udinator
a28bcfa485
[DV] Fix TB read responses ( #531 )
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Signed-off-by: Udi <udij@google.com>
2019-12-18 10:53:29 -08:00
udinator
7fef1b5afc
[DV] fix incorrect irq_seq handle name ( #525 )
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Signed-off-by: Udi <udij@google.com>
2019-12-16 16:18:47 -08:00
udinator
74e8c3fec6
[DV] update MISA csr yaml description ( #513 )
2019-12-16 13:39:00 -08:00
udinator
5d66a865cd
[DV] Enable sending multiple interrupts at once ( #519 )
2019-12-16 13:15:12 -08:00
udinator
c246a2aeb9
[DV] update override to riscv_asm_program gen in Makefile ( #520 )
2019-12-16 13:13:59 -08:00
udinator
8568e6b3b5
[DV] add support_unaligned_load_store setting ( #521 )
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Signed-off-by: Udi <udij@google.com>
2019-12-13 13:44:18 -08:00
udinator
f23b3f39fa
[DV] Fix xRET wait checks ( #515 )
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Signed-off-by: Udi <udij@google.com>
2019-12-12 11:28:16 -08:00
Taras Dulibianyk
50682bd314
RTL simulation scripts for Cadence tool was added
2019-12-04 07:32:27 +00:00
Taras Dulibianyk
9c981b198e
Pluseargs parsing was corrected
2019-12-03 16:23:50 +00:00
udinator
1a2270ce40
[DV] streamline Makefile gen flow ( #488 )
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Signed-off-by: Udi <udij@google.com>
2019-11-21 16:51:41 -08:00
udinator
1040d5e7e9
[DV] Update flow to match RISCV-DV changes ( #487 )
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Signed-off-by: Udi <udij@google.com>
2019-11-21 16:22:49 -08:00
udinator
2a01d1ce4c
[DV] Test accesses to higher privileged CSRs ( #483 )
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Signed-off-by: Udi <udij@google.com>
2019-11-21 11:18:39 -08:00
udinator
8112ba5a24
[DV] umode_tw test ( #481 )
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Signed-off-by: Udi <udij@google.com>
2019-11-18 13:43:02 -08:00
Pirmin Vogel
40d6368983
[dv] Remove clock gating primitive in dv/uvm/tb
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This commit removes a copy of the dummy clock gating primitive from
tree previously used for UVM-based DV. There is another, identical copy
of the same primitive in `shared/rtl` that can be used instead.
This resolves lowRISC/ibex#213 .
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2019-11-16 00:25:32 +01:00
udinator
c05634cfdf
[DV] Enable user-mode in DV environment, add basic tests ( #471 )
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Signed-off-by: Udi <udij@google.com>
2019-11-14 16:11:32 -08:00
udinator
7ea79ae366
[funct_cov] Fix GPR assignment bug ( #456 )
2019-11-12 10:07:12 -08:00
udinator
2a3c6c6430
[funct_cov] Update Makefile options for coverage ( #455 )
2019-11-11 15:07:20 -08:00
udinator
23589f5a91
[funct_cov] Update Ibex log parsing ( #453 )
2019-11-11 13:52:47 -08:00
udinator
502b5a951e
[DV] clean up stale TODOs ( #448 )
2019-11-04 16:52:01 -08:00
udinator
098fb7d847
[DV/flow] Integrate with RISCV-DV ( #446 )
2019-11-04 13:22:47 -08:00
udinator
e2ab24b9e3
[DV] Assert interrupt during write to MSTATUS and MIE ( #435 )
2019-10-31 11:14:53 -07:00
udinator
edf9371c6c
[DV] Increase number of resets in reset_test ( #418 )
2019-10-25 14:28:06 -07:00
udinator
d3c7b887d7
[DV] Increase number of illegal instructions generated ( #426 )
2019-10-25 14:00:22 -07:00
udinator
8e40f65582
[DV] Enable timer interrupts ( #415 )
2019-10-23 09:33:50 -07:00
udinator
beb40d89f6
[DV] Add interrupt wfi test to address coverage hole ( #410 )
2019-10-21 11:44:23 -07:00
udinator
fc80203af3
[DV] Debug_ebreak test fix ( #405 )
2019-10-16 17:44:47 -07:00
taoliug
1b71320230
Add RV32IM test ( #404 )
2019-10-16 10:15:49 -07:00
udinator
6b8b3762ec
[DV] Fix bugs in mem_error test to circumvent test deadlock ( #400 )
2019-10-15 15:19:36 -07:00
udinator
bbb688a2aa
[DV] Fix lint warnings ( #397 )
2019-10-14 10:20:28 -07:00
udinator
5972c63ba8
[DV] Let time-consuming checker tasks detect failures ( #395 )
2019-10-11 13:48:20 -07:00
udinator
ae82d61401
[DV] Add reset test ( #392 )
2019-10-10 13:01:32 -07:00
udinator
2ca1a6da21
[DV] Update csr description for U-mode changes ( #387 )
2019-10-10 09:18:48 -07:00
udinator
9824342c03
[DV] Added unaligned memory error test ( #378 )
2019-10-08 09:31:49 -07:00
udinator
84664077ee
[DV] Top level toggle coverage ( #371 )
2019-10-04 16:36:47 -07:00
udinator
48e604ab9e
[DV] Update ibex log regex ( #366 )
2019-10-02 13:16:47 -07:00
udinator
f2048ea8e4
[DV] Debug single step test ( #362 )
2019-10-01 16:39:32 -07:00
taoliug
b03ae4e2a7
[DV]Add Makefile target for functional coverage ( #358 )
2019-09-30 10:24:44 -07:00
udinator
074e637b11
[DV] Fix ovpsim compare issue ( #355 )
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* [DV] Fix ovpsim compare issue
* Update some test descriptions to avoid timeouts, update debug test
2019-09-27 17:45:58 -07:00
udinator
1615969bc1
[DV] Refactor debug stress stimulus to avoid race conditions ( #354 )
2019-09-25 19:08:05 -07:00
udinator
576d0ed76d
[DV] Basic performance test ( #352 )
2019-09-25 16:28:57 -07:00
udinator
6bae3f2d6f
Tighten debug stimulus assertion ( #351 )
2019-09-25 14:45:00 -07:00
udinator
ec02461b4a
[DV] Fix implemented_csr[] compile issue ( #346 )
2019-09-23 17:49:40 -07:00
udinator
9b967a5d97
[DV] Update implemented CSRs ( #345 )
2019-09-23 15:59:10 -07:00
udinator
717bf1ae02
Fix memory error test logic ( #344 )
2019-09-23 15:32:20 -07:00
